Abstract: Some embodiments include methods of forming BJTs. A first type doped region is formed within semiconductor material. First and second trenches are formed within the semiconductor material to pattern an array of pedestals, and the trenches are filled with electrically insulative material. An upper portion of the first type doped region is counter-doped to form a first stack having a second type doped region over a first type doped region, and an upper portion of the first stack is then counter-doped to form a second stack having a second type doped region between a pair of first type doped regions. Some embodiments include a BJT array. A base implant region is between a pair of emitter/collector implant regions. Electrically insulative material is adjacent the base implant region, and contains at least about 7×1016 atoms/cm3 of base implant region dopant.

Abstract: Some embodiments include methods of forming BJTs. A first type doped region is formed within semiconductor material. First and second trenches are formed within the semiconductor material to pattern an array of pedestals, and the trenches are filled with electrically insulative material. An upper portion of the first type doped region is counter-doped to form a first stack having a second type doped region over a first type doped region, and an upper portion of the first stack is then counter-doped to form a second stack having a second type doped region between a pair of first type doped regions. Some embodiments include a BJT array. A base implant region is between a pair of emitter/collector implant regions. Electrically insulative material is adjacent the base implant region, and contains at least about 7×1016 atoms/cm3 of base implant region dopant.

Abstract: Some embodiments include methods of forming BJTs. A first type doped region is formed within semiconductor material. First and second trenches are formed within the semiconductor material to pattern an array of pedestals, and the trenches are filled with electrically insulative material. An upper portion of the first type doped region is counter-doped to form a first stack having a second type doped region over a first type doped region, and an upper portion of the first stack is then counter-doped to form a second stack having a second type doped region between a pair of first type doped regions. Some embodiments include a BJT array. A base implant region is between a pair of emitter/collector implant regions. Electrically insulative material is adjacent the base implant region, and contains at least about 7×1016 atoms/cm3 of base implant region dopant.

Abstract: Some embodiments include methods of forming BJTs. A first type doped region is formed within semiconductor material. First and second trenches are formed within the semiconductor material to pattern an array of pedestals, and the trenches are filled with electrically insulative material. An upper portion of the first type doped region is counter-doped to form a first stack having a second type doped region over a first type doped region, and an upper portion of the first stack is then counter-doped to form a second stack having a second type doped region between a pair of first type doped regions. Some embodiments include a BJT array. A base implant region is between a pair of emitter/collector implant regions. Electrically insulative material is adjacent the base implant region, and contains at least about 7×1016 atoms/cm3 of base implant region dopant.

Abstract: A set bit in a phase change memory may be programmed to a reset bit using a series of pulses of increasing amplitude. An initial start pulse is applied. After the start pulse is applied, a check determines whether the bit has been reset. If not, a higher amplitude pulse is applied. Each time the pulse amplitude is to be incremented, a check determines whether a maximum safe pulse amplitude has been exceeded. The pulse amplitude is continually incremented until either the maximum is reached or all the bits to be programmed have been programmed into the correct reset state.

Abstract: A set bit in a phase change memory may be programmed to a reset bit using a series of pulses of increasing amplitude. An initial start pulse is applied. After the start pulse is applied, a check determines whether the bit has been reset. If not, a higher amplitude pulse is applied. Each time the pulse amplitude is to be incremented, a check determines whether a maximum safe pulse amplitude has been exceeded. The pulse amplitude is continually incremented until either the maximum is reached or all the bits to be programmed have been programmed into the correct reset state.

Abstract: A set bit in a phase change memory may be programmed to a reset bit using a series of pulses of increasing amplitude. An initial start pulse is applied. After the start pulse is applied, a check determines whether the bit has been reset. If not, a higher amplitude pulse is applied. Each time the pulse amplitude is to be incremented, a check determines whether a maximum safe pulse amplitude has been exceeded. The pulse amplitude is continually incremented until either the maximum is reached or all the bits to be programmed have been programmed into the correct reset state.

Abstract: A phase-change memory cell is formed by a phase-change memory element and by a selection element, which is formed in a semiconductor material body and is connected to the phase-change memory element. The phase-change memory element is made up of a calcogenic material layer and a heater. The selection element is in direct contact with the heater and extends through a dielectric region arranged on top of and contiguous to the semiconductor material body. A dielectric material layer is arranged on the dielectric region and houses a portion of the calcogenic material layer.

Abstract: A set bit in a phase change memory may be programmed to a reset bit using a series of pulses of increasing amplitude. An initial start pulse is applied. After the start pulse is applied, a check determines whether the bit has been reset. If not, a higher amplitude pulse is applied. Each time the pulse amplitude is to be incremented, a check determines whether a maximum safe pulse amplitude has been exceeded. The pulse amplitude is continually incremented until either the maximum is reached or all the bits to be programmed have been programmed into the correct reset state.

Abstract: A set bit in a phase change memory may be programmed to a reset bit using a series of pulses of increasing amplitude. An initial start pulse is applied. After the start pulse is applied, a check determines whether the bit has been reset. If not, a higher amplitude pulse is applied. Each time the pulse amplitude is to be incremented, a check determines whether a maximum safe pulse amplitude has been exceeded. The pulse amplitude is continually incremented until either the maximum is reached or all the bits to be programmed have been programmed into the correct reset state.

Abstract: A set bit in a phase change memory may be programmed to a reset bit using a series of pulses of increasing amplitude. An initial start pulse is applied. After the start pulse is applied, a check determines whether the bit has been reset. If not, a higher amplitude pulse is applied. Each time the pulse amplitude is to be incremented, a check determines whether a maximum safe pulse amplitude has been exceeded. The pulse amplitude is continually incremented until either the maximum is reached or all the bits to be programmed have been programmed into the correct reset state.