Patents by Inventor Federico Agustin ALTOLAGUIRRE
Federico Agustin ALTOLAGUIRRE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901892Abstract: A level shifter and a chip with the level shifter are shown. Between the input pair and the cross-coupled output pair, there are a first protection circuit and a second protection circuit. An overdrive voltage, which is double the nominal voltage of the level shifter plus a delta voltage, is applied to the level shifter. The first protection circuit has a first voltage-drop circuit that compensates for the delta voltage. The second protection circuit has a second voltage-drop circuit that compensates for the delta voltage.Type: GrantFiled: August 16, 2022Date of Patent: February 13, 2024Assignee: MEDIATEK INC.Inventors: Federico Agustin Altolaguirre, Hsin-Cheng Hsu
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Patent number: 11881847Abstract: A post driver and a chip with overdrive capability are shown. A first bias circuit is configured to provide a first voltage shift between the output terminal of the post driver and the gate terminal of the first p-channel metal-oxide-semiconductor (PMOS) transistor of a pull-up circuit when the pull-down circuit is enabled. A second bias circuit is configured to provide a second voltage shift between the output terminal of the post driver and the gate terminal of the first n-channel metal-oxide-semiconductor (NMOS) transistor of the pull-down circuit when the pull-up circuit is enabled. Accordingly, the PMOS transistors in the pull-up circuit and the NMOS transistors in the pull-down circuit are all well protected although they are powered by an overdrive voltage.Type: GrantFiled: July 12, 2022Date of Patent: January 23, 2024Assignee: MEDIATEK INC.Inventors: Federico Agustin Altolaguirre, Hsin-Cheng Hsu
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Publication number: 20230268925Abstract: A level shifter with high reliability is shown, which has a power multiplexer receiving a plurality of power voltage candidates to selectively output a selected power voltage. In response to a low-to-high transition of the input signal of the level shifter, the first output terminal of the level shifter is pulled up to the selected power voltage by the second pull-up device, and the first pull-down device pulls down the second output terminal of the level shifter to a low-voltage level corresponding to the selected power voltage. In response to a high-to-low transition of the input signal, the second output terminal of the level shifter is pulled up to the selected power voltage by the first pull-up device, and the second pull-down device pulls down the first output terminal of the level shifter to the low-voltage level corresponding to the selected power voltage.Type: ApplicationFiled: May 2, 2023Publication date: August 24, 2023Inventors: Hsin-Cheng HSU, Federico Agustin ALTOLAGUIRRE
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Patent number: 11716073Abstract: A chip with pad tracking having an input/output buffer (I/O buffer), a pad, and a bias circuit. The I/O buffer is powered by a first power and is coupled to the pad. The pad is coupled to the system power. The bias circuit generates a bias signal to be transferred to the I/O buffer to block a leakage path within the I/O buffer when the system power is on and the first power is off. The bias circuit is a voltage divider which generates a divided voltage as the bias signal. In an example, the bias circuit is powered by a second power that is independent from the first power and is not drawn from the pad. In another example, a power terminal of the bias circuit is coupled to an electrostatic discharging bus, and the pad is coupled to the electrostatic discharging bus through a diode.Type: GrantFiled: January 21, 2022Date of Patent: August 1, 2023Assignee: MEDIATEK INC.Inventors: Hsin-Cheng Hsu, Jui-Ming Chen, Federico Agustin Altolaguirre
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Patent number: 11695395Abstract: A level shifter with high reliability is shown, which has a cross-coupled pair and a pull-down pair. The cross-coupled pair couples a first power terminal to a first output terminal of the level shifter or a second output terminal of the level shifter. The pull-down pair has a first transistor and a second transistor, which are controlled according to an input signal of the level shifter. The first transistor is coupled between the second output terminal and a second power terminal, and the second transistor is coupled between the first output terminal and the second power terminal. A first voltage level coupled to the first power terminal is greater than a second voltage level coupled to the second power terminal, and the second voltage level is greater than the ground level.Type: GrantFiled: January 19, 2022Date of Patent: July 4, 2023Assignee: MEDIATEK INC.Inventors: Hsin-Cheng Hsu, Federico Agustin Altolaguirre
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Publication number: 20230081401Abstract: A post driver and a chip with overdrive capability are shown. A first bias circuit is configured to provide a first voltage shift between the output terminal of the post driver and the gate terminal of the first p-channel metal-oxide-semiconductor (PMOS) transistor of a pull-up circuit when the pull-down circuit is enabled. A second bias circuit is configured to provide a second voltage shift between the output terminal of the post driver and the gate terminal of the first n-channel metal-oxide-semiconductor (NMOS) transistor of the pull-down circuit when the pull-up circuit is enabled. Accordingly, the PMOS transistors in the pull-up circuit and the NMOS transistors in the pull-down circuit are all well protected although they are powered by an overdrive voltage.Type: ApplicationFiled: July 12, 2022Publication date: March 16, 2023Inventors: Federico Agustin ALTOLAGUIRRE, Hsin-Cheng HSU
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Publication number: 20230080713Abstract: A level shifter and a chip with the level shifter are shown. Between the input pair and the cross-coupled output pair, there are a first protection circuit and a second protection circuit. An overdrive voltage, which is double the nominal voltage of the level shifter plus a delta voltage, is applied to the level shifter. The first protection circuit has a first voltage-drop circuit that compensates for the delta voltage. The second protection circuit has a second voltage-drop circuit that compensates for the delta voltage.Type: ApplicationFiled: August 16, 2022Publication date: March 16, 2023Inventors: Federico Agustin ALTOLAGUIRRE, Hsin-Cheng HSU
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Publication number: 20220329232Abstract: A chip with pad tracking having an input/output buffer (I/O buffer), a pad, and a bias circuit. The I/O buffer is powered by a first power and is coupled to the pad. The pad is coupled to the system power. The bias circuit generates a bias signal to be transferred to the I/O buffer to block a leakage path within the I/O buffer when the system power is on and the first power is off. The bias circuit is a voltage divider which generates a divided voltage as the bias signal. In an example, the bias circuit is powered by a second power that is independent from the first power and is not drawn from the pad. In another example, a power terminal of the bias circuit is coupled to an electrostatic discharging bus, and the pad is coupled to the electrostatic discharging bus through a diode.Type: ApplicationFiled: January 21, 2022Publication date: October 13, 2022Inventors: Hsin-Cheng HSU, Jui-Ming CHEN, Federico Agustin ALTOLAGUIRRE
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Publication number: 20220329236Abstract: A level shifter with high reliability is shown, which has a cross-coupled pair and a pull-down pair. The cross-coupled pair couples a first power terminal to a first output terminal of the level shifter or a second output terminal of the level shifter. The pull-down pair has a first transistor and a second transistor, which are controlled according to an input signal of the level shifter. The first transistor is coupled between the second output terminal and a second power terminal, and the second transistor is coupled between the first output terminal and the second power terminal. A first voltage level coupled to the first power terminal is greater than a second voltage level coupled to the second power terminal, and the second voltage level is greater than the ground level.Type: ApplicationFiled: January 19, 2022Publication date: October 13, 2022Inventors: Hsin-Cheng HSU, Federico Agustin ALTOLAGUIRRE
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Patent number: 10177137Abstract: An electrostatic discharge (ESD) protection apparatus is provided. A first power rail provides first reference voltage. A second power rail provides a second reference voltage. A detection circuit generates a detection result according to whether ESD stress occurs on the first power rail. A first N-type MOSFET has its gate serving as a control terminal. A second N-type MOSFET has its gate serving as a second control node. An intermediate power rail provides an intermediate voltage between the first and the second reference voltages. A first switching circuit couples the first control node to the intermediate power rail or to the first power rail according to the detection result. A second switching circuit couples the second control node to the second power rail or to the first control node according to the detection result.Type: GrantFiled: February 8, 2018Date of Patent: January 8, 2019Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Federico Agustin Altolaguirre, Yen-Hung Yeh, Po-Ya Lai
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Patent number: 10171068Abstract: An input interface circuit is provided. When a pad voltage is higher than a default operating voltage, a clamping circuit maintains the voltage at a first node at the default operating voltage. A first inverter is coupled between the first node and a second node. A voltage of a third node is adjusted along with the pad voltage (input end of a high-voltage buffering circuit) and the voltage at the second node, and causes the voltage at the third node has a same voltage change trend as the pad voltage. A second inverter is coupled between the third node and a fourth node. A voltage recovery circuit has its input end coupled to the fourth node and its output end coupled to the third node, and selectively couples the third node to a power line or a ground line according to the voltage at the fourth node.Type: GrantFiled: March 8, 2018Date of Patent: January 1, 2019Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Federico Agustin Altolaguirre, Yen-Hung Yeh
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Patent number: 10147717Abstract: In the disclosure, an electrostatic discharge (ESD) protection circuit is coupled between a first power rail and a second power rail to discharge any ESD stress. The ESD protection circuit includes a detection circuit, a triggering circuit, and a dual silicon controlled rectifier (DSCR) device. When an ESD stresses is being applied to the first or second power rail, the detection circuit may first detect the ESD stresses and output a detection signal to the triggering circuit. The triggering circuit generates a triggering signal based on the detection signal and the polarity of the ESD stress. Then, the DSCR device is symmetrically triggered based on the triggering signal received at a common node between at least two transistors of the same type. The exemplary ESD protection circuit may be implemented in nanoscale manufactured integrated circuit and achieve good ESD robustness while maintaining low standby leakage current and relatively small silicon footprint.Type: GrantFiled: August 26, 2016Date of Patent: December 4, 2018Assignee: Novatek Microelectronics Corp.Inventors: Federico Agustin Altolaguirre, Ming-Dou Ker, Tzu-Chien Tzeng, Ju-Lin Huang
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Patent number: 9722097Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a well region disposed in the substrate; an isolation structure surrounding an active region in the well region; a source region disposed in the well region; a drain region disposed in the well region; a second conductive type first doped region disposed in the well region and disposed along a periphery of the active region; a second conductive type second doped region disposed in the well region and under the source region, the drain region and the second conductive type first doped region, wherein the second conductive type second doped region is in direct contact with the second conductive type first doped region; a source electrode; a drain electrode and a gate electrode. The present disclosure also provides a method for manufacturing the semiconductor device.Type: GrantFiled: September 16, 2015Date of Patent: August 1, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Karuna Nidhi, Federico Agustin Altolaguirre, Ming-Dou Ker, Geeng-Lih Lin
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Publication number: 20170077316Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a well region disposed in the substrate; an isolation structure surrounding an active region in the well region; a source region disposed in the well region; a drain region disposed in the well region; a second conductive type first doped region disposed in the well region and disposed along a periphery of the active region; a second conductive type second doped region disposed in the well region and under the source region, the drain region and the second conductive type first doped region, wherein the second conductive type second doped region is in direct contact with the second conductive type first doped region; a source electrode; a drain electrode and a gate electrode. The present disclosure also provides a method for manufacturing the semiconductor device.Type: ApplicationFiled: September 16, 2015Publication date: March 16, 2017Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Karuna NIDHI, Federico Agustin ALTOLAGUIRRE, Ming-Dou KER, Geeng-Lih LIN
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Publication number: 20170069618Abstract: In the disclosure, an electrostatic discharge (ESD) protection circuit is coupled between a first power rail and a second power rail to discharge any ESD stress. The ESD protection circuit includes a detection circuit, a triggering circuit, and a dual silicon controlled rectifier (DSCR) device. When an ESD stresses is being applied to the first or second power rail, the detection circuit may first detect the ESD stresses and output a detection signal to the triggering circuit. The triggering circuit generates a triggering signal based on the detection signal and the polarity of the ESD stress. Then, the DSCR device is symmetrically triggered based on the triggering signal received at a common node between at least two transistors of the same type. The exemplary ESD protection circuit may be implemented in nanoscale manufactured integrated circuit and achieve good ESD robustness while maintaining low standby leakage current and relatively small silicon footprint.Type: ApplicationFiled: August 26, 2016Publication date: March 9, 2017Applicant: Novatek Microelectronics Corp.Inventors: Federico Agustin Altolaguirre, Ming-Dou Ker, Tzu-Chien Tzeng, Ju-Lin Huang
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Patent number: 9437591Abstract: A cross-domain electrostatic protection device having four embedded silicon controlled rectifiers (a QSCR structure) embedded in a single cell. Two grounded-gate NMOS transistors are embedded into the cross-domain electrostatic protection device for reducing trigger voltage of the QSCR structure. Furthermore, an external trigger circuit and a bias circuit are applied to the cross-domain electrostatic protection device to reduce trigger voltage of the QSCR structure and leakage current.Type: GrantFiled: September 9, 2015Date of Patent: September 6, 2016Assignee: Vanguard International Semiconductor CorporationInventors: Karuna Nidhi, Federico Agustin Altolaguirre, Ming-Dou Ker, Geeng-Lih Lin
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Patent number: 8773826Abstract: A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation.Type: GrantFiled: August 29, 2012Date of Patent: July 8, 2014Assignee: Amazing Microelectronic Corp.Inventors: Federico Agustin Altolaguirre, Ming-Dou Ker, Ryan Hsin-Chin Jiang
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Publication number: 20140063663Abstract: A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation.Type: ApplicationFiled: August 29, 2012Publication date: March 6, 2014Inventors: Federico Agustin ALTOLAGUIRRE, Ming-Dou Ker, Ryan Hsin-Chin Jiang