Abstract: There is provided a communication receiver comprising: an input for receiving a radio frequency, RF, input signal; and at least one finite impulse response, FIR, discrete time filter, DTF. The at least one FIR DTF comprises: an input circuit comprising an input port for sampling the RF input signal at a sampling frequency that is comparable to the input RF input signal; and N parallel branches, each branch having a set of input unit sampling capacitances, where each unit sampling capacitance is independently selectively coupleable to an output summing node. The input circuit is configured to convert an equivalent input impedance of the at least one FIR DTF around the sampling frequency to a real impedance.

Abstract: A discrete time filter, DTF, is described that comprises a summing node; N parallel branches, each branch having a set of input unit sampling capacitances where each unit sampling capacitance is independently selectively coupleable to the summing node; and an output capacitance connected to the summing node. The output capacitance has a value equal to a sum of the sampling capacitances that are to be selectively connected to the summing node; and the discrete time filter further comprises an inductance connected between the summing node and the output capacitance.

Abstract: There is provided a communication receiver comprising: an input for receiving a radio frequency, RF, input signal; and at least one finite impulse response, FIR, discrete time filter, DTF. The at least one FIR DTF comprises: an input circuit comprising an input port for sampling the RF input signal at a sampling frequency that is comparable to the input RF input signal; and N parallel branches, each branch having a set of input unit sampling capacitances, where each unit sampling capacitance is independently selectively coupleable to an output summing node. The input circuit is configured to convert an equivalent input impedance of the at least one FIR DTF around the sampling frequency to a real impedance.

Abstract: A discrete time filter, DTF, is described that comprises a summing node; N parallel branches, each branch having a set of input unit sampling capacitances where each unit sampling capacitance is independently selectively coupleable to the summing node; and an output capacitance connected to the summing node. The output capacitance has a value equal to a sum of the sampling capacitances that are to be selectively connected to the summing node; and the discrete time filter further comprises an inductance connected between the summing node and the output capacitance.

Abstract: A mixer circuit comprises an input stage arranged to convert an input voltage signal received at an input of the mixer circuit into at least one current signal, and a frequency conversion stage comprising at least one switching element arranged to convert a signal component of the at least one current signal from an input frequency to a output frequency. The input stage comprises at least one resistance connected between the input of the mixer circuit and the at least one switching element. The at least one switching element and the at least one resistance are arranged such that the at least one switching element comprises a ‘turn-on’ resistance that exhibits a resistivity that is a factor less than the at least one resistance connected thereto.

Abstract: An amplifier circuit for amplifying a differential input signal includes a first feedback resistance, a second feedback resistance, first transconductance circuitry, and second transconductance circuitry. The first feedback resistance is connected between a first input node and a first output node of the amplifier circuit. The second feedback resistance is connected between a second input node and a second output node of the amplifier circuit. The first transconductance circuitry is arranged to inject a transconductance current at a point along the first feedback resistance, and is configurable to vary the point along the first feedback resistance where the transconductance current is injected. The second transconductance circuitry is arranged to inject another transconductance current at a point along the second feedback resistance, and is configurable to vary the point along the second feedback resistance where the another transconductance current is injected.

Abstract: An amplifier circuit for amplifying a differential input signal includes a first feedback resistance, a second feedback resistance, first transconductance circuitry, and second transconductance circuitry. The first feedback resistance is connected between a first input node and a first output node of the amplifier circuit. The second feedback resistance is connected between a second input node and a second output node of the amplifier circuit. The first transconductance circuitry is arranged to inject a transconductance current at a point along the first feedback resistance, and is configurable to vary the point along the first feedback resistance where the transconductance current is injected. The second transconductance circuitry is arranged to inject another transconductance current at a point along the second feedback resistance, and is configurable to vary the point along the second feedback resistance where the another transconductance current is injected.

Abstract: A mixer circuit comprises an input stage arranged to convert an input voltage signal received at an input of the mixer circuit into at least one current signal, and a frequency conversion stage comprising at least one switching element arranged to convert a signal component of the at least one current signal from an input frequency to a output frequency. The input stage comprises at least one resistance connected between the input of the mixer circuit and the at least one switching element. The at least one switching element and the at least one resistance are arranged such that the at least one switching element comprises a ‘turn-on’ resistance that exhibits a resistivity that is a factor less than the at least one resistance connected thereto.

Abstract: An amplifier circuit for amplifying an input signal received at an input node of the amplifier circuit. The amplifier circuit comprises a feedback resistance connected between the input node of the amplifier circuit and an output node of the amplifier circuit. Transconductance circuitry is arranged to inject a transconductance current at a point along the feedback resistance. The transconductance circuitry is configurable to vary the point along the feedback resistance where the transconductance current is injected.

Abstract: An amplifier circuit for amplifying an input signal received at an input node of the amplifier circuit. The amplifier circuit comprises a feedback resistance connected between the input node of the amplifier circuit and an output node of the amplifier circuit. Transconductance circuitry is arranged to inject a transconductance current at a point along the feedback resistance. The transconductance circuitry is configurable to vary the point along the feedback resistance where the transconductance current is injected.

Abstract: A circuit for synthesising a negative resistance, comprising first and second active devices, the first device having a control terminal connected to a first node, and the second device having a current flow terminal connected to the first node, and the first and second devices interacting with each other such that the circuit synthesises a negative resistance.

Abstract: A circuit for synthesising a negative resistance, comprising first and second active devices, the first device having a control terminal connected to a first node, and the second device having a current flow terminal connected to the first node, and the first and second devices interacting with each other such that the circuit synthesises a negative resistance.

Abstract: A transconductance circuit, comprising: first and second field effect transistors, each having a drain, a source and a gate; wherein the first transistor is in a first current flow path between first and second nodes of the circuit, and is biased so as to operate in a saturation region of its transfer characteristic; the second field effect transistor is in a second current flow path between the first and second nodes of the circuit and is biased so as to operate in a linear region of its transfer characteristic; the gate of the first and second transistors are connected to receive an input signal; and wherein the second transistor is further in series with a voltage modulator adapted to reduce the drain-source voltage occurring across the second transistor in response to increased current flow in the second transistor.