Patents by Inventor Federico Ardanaz
Federico Ardanaz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11809250Abstract: A scheme to improve performance of power-constrained computers, comprising a heterogeneous mix of compute elements, by dynamically reacting to changes in the switching capacitance that present workload induces in each heterogeneous compute element and learning the coefficients of a power-frequency model for each compute element for the present workload. At each time step, the scheme forecasts a maximum frequency that the compute element can run at without exceeding an input power limit for a given workload. The scheme rapidly re-learns coefficients of the power model and rapidly adapts the frequency as the workload's characteristics shift ensuring that compute elements run at the maximum frequency they can while not exceeding the input power limit.Type: GrantFiled: October 19, 2020Date of Patent: November 7, 2023Assignee: Intel CorporationInventors: Ali Mohammad, Asma Al-Rawi, Ujjwal Gupta, Federico Ardanaz, Jonathan Eastep
-
Patent number: 11650652Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.Type: GrantFiled: June 24, 2021Date of Patent: May 16, 2023Assignee: INTEL CORPORATIONInventors: Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco, Ramkumar Nagappan, Alan B. Kyker
-
Patent number: 11194373Abstract: Various embodiments comprise prioritizing frequency allocations in thermally- or power-constrained computing devices. Computer elements may be assigned ‘weights’ based on their priorities. The computer elements with higher weights may receive higher frequency allocations to assure they receive priority in processing more quickly. The computer elements with lower weights may receive lower frequency allocations and suffer a slowdown in their processing. Elements with the same weight may be grouped together for the purpose of frequency allocation.Type: GrantFiled: April 20, 2020Date of Patent: December 7, 2021Assignee: Intel CorporationInventors: Asma Al-Rawi, Federico Ardanaz, Jonathan M. Eastep, Nikhil Gupta, Ankush Varma, Krishnakanth V. Sistla, Ian M. Steiner
-
Publication number: 20210325952Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.Type: ApplicationFiled: June 24, 2021Publication date: October 21, 2021Applicant: INTEL CORPORATIONInventors: Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco, Ramkumar Nagappan, Alan B. Kyker
-
Patent number: 11144085Abstract: An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.Type: GrantFiled: June 23, 2017Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Asma H. Al-Rawi, Federico Ardanaz, Jonathan M. Eastep, Dorit Shapira, Krishnakanth Sistla, Nikhil Gupta, Vasudevan Srinivasan, Chris MacNamara
-
Patent number: 11061463Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.Type: GrantFiled: August 29, 2017Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco, Ramkumar Nagappan, Alan B. Kyker
-
Patent number: 11061460Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for Thermal Design Power (TDP) rebalancing among thermally-coupled processors and non-thermally-coupled processors, providing computing efficiency or homogeneity with respect to, including but not limited to, thermal requirements, power consumption, and processor operations. The TDP rebalancing may include implementing management circuitry and configuration control circuitry. Other embodiments may be described and claimed.Type: GrantFiled: June 28, 2019Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Fuat Keceli, Tozer J. Bandorawalla, Grant McFarland, Jonathan M. Eastep, Federico Ardanaz
-
Patent number: 11048313Abstract: Described herein are automated hierarchical feed-back driven control mechanisms and methods, including an apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to receive a system operating characteristic guidance. The second circuitry may be operable to provide one or more manufacturing characteristics. The third circuitry may be operable to store one or more system operating characteristics based upon the system operating characteristic guidance and the one or more manufacturing characteristics.Type: GrantFiled: March 29, 2019Date of Patent: June 29, 2021Assignee: Intel CorporationInventors: Siddhartha Jana, Federico Ardanaz, Jonathan M. Eastep, Yaxin Shui, Keith Underwood
-
Publication number: 20210124404Abstract: A scheme to improve performance of power-constrained computers, comprising a heterogeneous mix of compute elements, by dynamically reacting to changes in the switching capacitance that present workload induces in each heterogeneous compute element and learning the coefficients of a power-frequency model for each compute element for the present workload. At each time step, the scheme forecasts a maximum frequency that the compute element can run at without exceeding an input power limit for a given workload. The scheme rapidly re-learns coefficients of the power model and rapidly adapts the frequency as the workload's characteristics shift ensuring that compute elements run at the maximum frequency they can while not exceeding the input power limit.Type: ApplicationFiled: October 19, 2020Publication date: April 29, 2021Applicant: Intel CorporationInventors: Ali Mohammad, Asma Al-Rawi, Ujjwal Gupta, Federico Ardanaz, Jonathan Eastep
-
Patent number: 10908668Abstract: Systems, apparatuses and methods may provide for determining, from a program comprising graphs of parallel operations and dependencies, an estimation of a droop risk associated with execution of the graphs by a load. A risk signal may be outputted based on the estimation. The risk signal may be associated with an adjustment in an output voltage of a voltage regulator and the output voltage is to be provided to the load.Type: GrantFiled: December 29, 2017Date of Patent: February 2, 2021Assignee: Intel CorporationInventors: Fuat Keceli, Jonathan Eastep, Kelly Livingston, Federico Ardanaz
-
Publication number: 20200319693Abstract: Various embodiments comprise prioritizing frequency allocations in thermally- or power-constrained computing devices. Computer elements may be assigned ‘weights’ based on their priorities. The computer elements with higher weights may receive higher frequency allocations to assure they receive priority in processing more quickly. The computer elements with lower weights may receive lower frequency allocations and suffer a slowdown in their processing. Elements with the same weight may be grouped together for the purpose of frequency allocation.Type: ApplicationFiled: April 20, 2020Publication date: October 8, 2020Applicant: Intel CorporationInventors: Asma Al-Rawi, Federico Ardanaz, Jonathan M. Eastep, Nikhil Gupta, Ankush Varma, Krishnakanth V. Sistla, Ian M. Steiner
-
Publication number: 20200310515Abstract: Described herein are automated hierarchical feed-back driven control mechanisms and methods, including an apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to receive a system operating characteristic guidance. The second circuitry may be operable to provide one or more manufacturing characteristics. The third circuitry may be operable to store one or more system operating characteristics based upon the system operating characteristic guidance and the one or more manufacturing characteristics.Type: ApplicationFiled: March 29, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: Siddhartha Jana, Federico Ardanaz, Jonathan M. Eastep, Yaxin Shui, Keith Underwood
-
Patent number: 10719320Abstract: An apparatus is provided which comprises: a component; a voltage generator to supply load current to the component; first one or more circuitries to predict that the load current is to increase from a first time; and second one or more circuitries to, in anticipation of the increase in the load current from the first time, cause the component to execute first instructions during a time period that occurs prior to the first time.Type: GrantFiled: July 31, 2017Date of Patent: July 21, 2020Assignee: Intel CorporationInventors: Federico Ardanaz, Roger Gramunt, Jesus Corbal, Dennis R. Bradford, Jonathan M. Eastep
-
Patent number: 10684663Abstract: Systems, apparatuses and methods may provide for receiving indicator data associated with activity of a load. Additionally, an estimation of a rate of change of a current of the load with respect to time may be determined from the indicator data. Moreover, a boost signal may be selectively output to a voltage regulator when the estimation of the rate of change is greater than a first amount. The boost signal may be associated with an adjustment in an output voltage of the voltage regulator and the output voltage may be provided to the load.Type: GrantFiled: December 28, 2017Date of Patent: June 16, 2020Assignee: Intel CorporationInventors: Kelly Livingston, Federico Ardanaz, Dmitry Lukianchenko, Fuat Keceli, Jonathan Eastep
-
Patent number: 10627885Abstract: Various embodiments comprise prioritizing frequency allocations in thermally- or power-constrained computing devices. Computer elements may be assigned ‘weights’ based on their priorities. The computer elements with higher weights may receive higher frequency allocations to assure they receive priority in processing more quickly. The computer elements with lower weights may receive lower frequency allocations and suffer a slowdown in their processing. Elements with the same weight may be grouped together for the purpose of frequency allocation.Type: GrantFiled: January 9, 2018Date of Patent: April 21, 2020Assignee: Intel CorporationInventors: Asma Al-Rawi, Federico Ardanaz, Jonathan M. Eastep, Nikhil Gupta, Ankush Varma, Krishnakanth V. Sistla, Ian M. Steiner
-
Patent number: 10620687Abstract: Methods and apparatus to provide a hybrid power management approach are described. Some embodiments redefine the interface to Power Control Unit (PCU) allowing a hybrid implementation where software running on CPU (Central Processing Unit, also referred to herein interchangeably as “processor”) cores performs more of the work for power management, enabling the PCU to remain as a simple or regular microcontroller. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 22, 2014Date of Patent: April 14, 2020Assignee: Intel CorporationInventors: Jonathan M. Eastep, Richard J. Greco, Federico Ardanaz
-
Publication number: 20190324517Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for Thermal Design Power (TDP) rebalancing among thermally-coupled processors and non-thermally-coupled processors, providing computing efficiency or homogeneity with respect to, including but not limited to, thermal requirements, power consumption, and processor operations. The TDP rebalancing may include implementing management circuitry and configuration control circuitry. Other embodiments may be described and claimed.Type: ApplicationFiled: June 28, 2019Publication date: October 24, 2019Inventors: Fuat Keceli, Tozer J. Bandorawalla, Grant McFarland, Jonathan M. Eastep, Federico Ardanaz
-
Patent number: 10261904Abstract: Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.Type: GrantFiled: December 7, 2017Date of Patent: April 16, 2019Assignee: Intel CorporationInventors: Chunhui Zhang, George Z. Chrysos, Edward T. Grochowski, Ramacharan Sundararaman, Chung-Lun Chan, Federico Ardanaz
-
Publication number: 20190095122Abstract: According to various aspects, a computing system may include one or more first memories of a first memory type and one or more second memories of a second memory type different from the first memory type and a memory controller. The memory controller may be configured to receive telemetry data associated with at least one of the one or more first memories and the one or more second memories, execute a data transfer between the one or more first memories and the one or more second memories in a first operation mode of the memory controller, suspend a data transfer between the one or more first memories and the one or more second memories in a second operation mode of the memory controller, and switch between the first operation mode and the second operation mode based on the telemetry data.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Inventors: Francesc Guim Bernat, Kshitij Doshi, Daniel Rivas Barragan, Federico Ardanaz, Suraj Prabhakaran
-
Patent number: 10223171Abstract: Systems, apparatuses and methods may provide for obtaining, by a system level reallocator in a plurality of reallocators arranged in a hierarchical tree, resource budget information. Additionally, application performance information may be obtained by at least one of the plurality of reallocators. Moreover, a performance imbalance between a plurality of compute subtrees associate with the application performance information may be reduced by the at least one of the plurality of reallocators and based at least in part on the resource budget information and the application performance information.Type: GrantFiled: March 25, 2016Date of Patent: March 5, 2019Assignee: Intel CorporationInventors: Stephanie Labasan, Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco