Patents by Inventor Federico Frego

Federico Frego has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250253213
    Abstract: An integrated circuit (IC) package and assembly includes a stacked arrangement of one or more IC die to leverage additional functionality in a standard package width. Active IC die and high voltage IC capacitors may be stacked in various arrangements to minimize the footprint and width of the IC package. The die are interconnected with each other and a lead frame with wire bonds, silicon vias or other interconnections. Various bond pad configurations are used to interconnect the die. The stacked arrangement of the IC die reduces the width of the supporting lead frame and reduces the overall footprint of the IC package.
    Type: Application
    Filed: February 2, 2024
    Publication date: August 7, 2025
    Applicant: Allegro MicroSystems, LLC
    Inventors: Andrew Thompson, Federico Frego
  • Publication number: 20230042407
    Abstract: Semiconductor devices are arranged in a chain extending in a longitudinal direction have mutually facing end sides transverse the longitudinal direction and are coupled via tie bars located at the mutually facing end sides. The tie bars are provided with anchoring tips penetrating into an insulating package at mutually facing end sides of the devices. The tie bars can be deformed to extract the anchoring tips from the insulating package at the mutually facing end sides of the devices. Individual singulated devices are thus produced in response to the anchoring tips being extracted from the mutually facing end sides of the devices.
    Type: Application
    Filed: August 1, 2022
    Publication date: February 9, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventors: Paolo CASATI, Federico FREGO
  • Publication number: 20190181076
    Abstract: A method of producing leadframes for semiconductor devices comprises: providing a plurality of electrically-conductive plates, forming in the electrically conductive plates homologous passageway patterns according to a desired semiconductor device leadframe pattern, joining together the plurality of plates with the homologous passageway patterns formed therein mutually in register by producing a multilayered leadframe exhibiting the desired leadframe pattern and a thickness which is the sum of the thicknesses of the plates in the plurality of electrically-conductive plates.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 13, 2019
    Inventors: Dario VITELLO, Fabio MARCHISI, Alberto ARRIGONI, Federico FREGO, Federico Giovanni ZIGLIOLI, Paolo CREMA
  • Patent number: 9922947
    Abstract: Various embodiments provide a bonding pad structure that is capable of handling increased bonding loads. In one embodiment, the bonding pad structure includes a continuous metal layer, a first discontinuous metal layer, a second discontinuous metal layer, and dielectric material. The first discontinuous metal layer and the second discontinuous metal layer each include a plurality of holes that are arranged in a pattern. The plurality of holes of the first discontinuous metal layer overlaps at least two of the plurality of holes of the second discontinuous metal layer. The dielectric material is formed between the metal layers and fills the plurality of holes of the first and second discontinuous metal layers.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: March 20, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Dario Vitello, Federico Frego, Salvatore Latino
  • Publication number: 20170317039
    Abstract: Various embodiments provide a bonding pad structure that is capable of handling increased bonding loads. In one embodiment, the bonding pad structure includes a continuous metal layer, a first discontinuous metal layer, a second discontinuous metal layer, and dielectric material. The first discontinuous metal layer and the second discontinuous metal layer each include a plurality of holes that are arranged in a pattern. The plurality of holes of the first discontinuous metal layer overlaps at least two of the plurality of holes of the second discontinuous metal layer. The dielectric material is formed between the metal layers and fills the plurality of holes of the first and second discontinuous metal layers.
    Type: Application
    Filed: April 28, 2016
    Publication date: November 2, 2017
    Inventors: Dario Vitello, Federico Frego, Salvatore Latino