Abstract: A processing system includes a communication system and a processing core configured to generate write requests. A circuit has associated a slave interface circuit configured to manage an address sub-range and selectively forward write requests addressed to a given address. Configuration data specifies whether the given address is protected/unprotected and locked/unlocked. In response to a received write request, address and data are extracted and a determination based on the configuration data is made as to whether the extracted address is protected/unprotected, and locked/unlocked. When the extracted address is unprotected or unlocked, the slave interface forwards the write request. When the extracted address is protected and locked, the slave interface generates an unlock signal in response to a comparison of the extracted address with the extracted data, with the unlock signal being asserted when the extracted data satisfy a predetermined rule with respect to the extracted address.

Abstract: A non-volatile memory receives a data read request from a processing core of a plurality of processing cores. The read request is directed to a data partition of a non-volatile memory. The non-volatile memory determines whether to process the read request using read-while-write collision management. When it is determined to process the read request using read-while-write collision management, an address associated with the read request is stored in an address register of a set of registers associated with the processing core. Write operations directed to the data partition are suspended. A read operation associated with the read request is executed while the write operations are suspended and data responsive to the read operation is stored in one or more data registers of the set of registers. The data stored in the one or more data registers of the set of registers is provided to the processing core.

Abstract: A slave provides second data bits and ECC bits in response to a master read request. First data bits are generated by selecting between the second data bits and third data bits produced from error correcting the second data bits. The third data bits are generated with a delay of one clock cycle with respect to the second data bits. If an address of the read request is stored to a memory, a control signal is set indicating that the first data bits are invalid and this drives selection of the third data bits (with the first data bits now being valid in a following clock cycle). If an error signal is asserted when the address is not stored to the memory, action is taken to store the address to the memory and a further control signal is set to indicate that the read request should be repeated.

Abstract: A processing system includes a communication system and a processing core configured to generate write requests. A circuit has associated a slave interface circuit configured to manage an address sub-range and selectively forward write requests addressed to a given address. Configuration data specifies whether the given address is protected/unprotected and locked/unlocked. In response to a received write request, address and data are extracted and a determination based on the configuration data is made as to whether the extracted address is protected/unprotected, and locked/unlocked. When the extracted address is unprotected or unlocked, the slave interface forwards the write request. When the extracted address is protected and locked, the slave interface generates an unlock signal in response to a comparison of the extracted address with the extracted data, with the unlock signal being asserted when the extracted data satisfy a predetermined rule with respect to the extracted address.

Abstract: A non-volatile memory receives a data read request from a processing core of a plurality of processing cores. The read request is directed to a data partition of a non-volatile memory. The non-volatile memory determines whether to process the read request using read-while-write collision management. When it is determined to process the read request using read-while-write collision management, an address associated with the read request is stored in an address register of a set of registers associated with the processing core. Write operations directed to the data partition are suspended. A read operation associated with the read request is executed while the write operations are suspended and data responsive to the read operation is stored in one or more data registers of the set of registers. The data stored in the one or more data registers of the set of registers is provided to the processing core.

Abstract: In an embodiment, a method includes receiving, between a positive input terminal and a negative input terminal, a supply voltage, receiving a data signal, generating, by a voltage generator in a branch of a plurality of branches, a branch current as a function of a respective driving signal and of a regulated voltage, each branch connected between the positive input terminal and the negative input terminal, selectively activating the voltage generator as a function of a respective enabling signal and providing, between a positive output terminal and a negative output terminal, the regulated voltage to one or more driving circuits.

Abstract: In an embodiment, a method includes receiving, between a positive input terminal and a negative input terminal, a supply voltage, receiving a data signal, generating, by a voltage generator in a branch of a plurality of branches, a branch current as a function of a respective driving signal and of a regulated voltage, each branch connected between the positive input terminal and the negative input terminal, selectively activating the voltage generator as a function of a respective enabling signal and providing, between a positive output terminal and a negative output terminal, the regulated voltage to one or more driving circuits.

Abstract: A voltage regulator and a phase change memory are disclosed. In an embodiment a phase-change memory includes an array of a plurality of phase-change memory cells, an address decoder configured for receiving an address signal and selecting a sub-area in the array of the plurality of memory cells, the selected sub-area having a given number of bits of a data signal and a writing circuit including a control circuit configured for receiving the data signal and determining, for each memory cell in the selected sub-area, whether a respective bit of the data signal indicates that the memory cell is to be changed from the amorphous state to the polycrystalline state and one or more driving circuits supplied via a regulated voltage and configured for applying the set current for the first interval to the memory cells that are to be changed from the amorphous state to the polycrystalline state.

Abstract: A method for programming a phase-change-memory device of a differential type comprises, in a first programming mode, supplying, during a first time interval, a same first programming current, of a type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said first programming current; and, in a second programming mode, supplying, during a second time interval, a same second programming current, of the other type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said second programming current, thus completing, in just two time steps, writing of a logic word in the memory device.

Abstract: A circuit, for managing operations for accessing a flash memory on the basis of requests received from a main CPU and from an auxiliary CPU, may be configured to: associate with the main CPU, a higher access priority to the flash memory than the access priority of the auxiliary CPU; command, in the absence of further requests for accessing the flash memory, the access to the flash memory for the main or auxiliary CPU which has initiated a first access request; verify, following a receipt of a second access request, the access priority associated with this second access request; suspend one of the first or the second access request having lower priority; and authorize the other of the first or the second access request having higher priority.

Abstract: A voltage regulator and a phase change memory are disclosed. In an embodiment a phase-change memory includes an array of a plurality of phase-change memory cells, an address decoder configured for receiving an address signal and selecting a sub-area in the array of the plurality of memory cells, the selected sub-area having a given number of bits of a data signal and a writing circuit including a control circuit configured for receiving the data signal and determining, for each memory cell in the selected sub-area, whether a respective bit of the data signal indicates that the memory cell is to be changed from the amorphous state to the polycrystalline state and one or more driving circuits supplied via a regulated voltage and configured for applying the set current for the first interval to the memory cells that are to be changed from the amorphous state to the polycrystalline state.

Abstract: A method for programming a phase-change-memory device of a differential type comprises, in a first programming mode, supplying, during a first time interval, a same first programming current, of a type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said first programming current; and, in a second programming mode, supplying, during a second time interval, a same second programming current, of the other type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said second programming current, thus completing, in just two time steps, writing of a logic word in the memory device.

Abstract: A circuit, for managing operations for accessing a flash memory on the basis of requests received from a main CPU and from an auxiliary CPU, may be configured to: associate with the main CPU, a higher access priority to the flash memory than the access priority of the auxiliary CPU; command, in the absence of further requests for accessing the flash memory, the access to the flash memory for the main or auxiliary CPU which has initiated a first access request; verify, following a receipt of a second access request, the access priority associated with this second access request; suspend one of the first or the second access request having lower priority; and authorize the other of the first or the second access request having higher priority.

Abstract: A circuit, for managing operations for accessing a flash memory on the basis of requests received from a main CPU and from an auxiliary CPU, may be configured to: associate with the main CPU, a higher access priority to the flash memory than the access priority of the auxiliary CPU; command, in the absence of further requests for accessing the flash memory, the access to the flash memory for the main or auxiliary CPU which has initiated a first access request; verify, following a receipt of a second access request, the access priority associated with this second access request; suspend one of the first or the second access request having lower priority; and authorize the other of the first or the second access request having higher priority.

Abstract: A circuit, for managing operations for accessing a flash memory on the basis of requests received from a main CPU and from an auxiliary CPU, may be configured to: associate with the main CPU, a higher access priority to the flash memory than the access priority of the auxiliary CPU; command, in the absence of further requests for accessing the flash memory, the access to the flash memory for the main or auxiliary CPU which has initiated a first access request; verify, following a receipt of a second access request, the access priority associated with this second access request; suspend one of the first or the second access request having lower priority; and authorize the other of the first or the second access request having higher priority.