Abstract: The present disclosure provides an array substrate and a display panel. The array substrate includes a substrate, a transistor and a first light-shielding portion disposed at a side of the substrate; and the first light-shielding portion is disposed between a source and an active layer, and between a drain and the active layer. An orthographic projection of the first light-shielding portion on the substrate covers an orthographic projection of the channel region on the substrate, and exceeds a range of the orthographic projection range of the channel region on the substrate, so as to shield reflected light from the metal layer where the source and the drain are located.

Abstract: The present application provides a thin film transistor and a display panel. An active layer of the thin film transistor includes at least two semiconductor layers stacked. Conductivity types of channel regions of adjacent two of the semiconductor layers are same. Doping concentrations of same elements in semiconductor materials of the adjacent two of the semiconductor layers are different. A homotypic heterostructure is formed after the adjacent two of the semiconductor layers contact, thereby improving a mobility of carriers.

Abstract: The embodiment of the present application discloses a liquid crystal display panel, the liquid crystal display panel includes a first substrate and a second substrate disposed opposite to each other. A frame sealant and a boss contacting each other are disposed in a frame sealant region, and the frame sealant at least partially overlaps the boss in a film thickness direction. A boss cooperating with the frame sealant to perform a sealing function is disposed in the frame sealant region. The boss reduces a volume of the frame sealant and lowers a time required for curing the frame sealant to improve a productivity.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes a substrate, a first metal layer, a photosensitive unit, and a second metal layer. The first metal layer is disposed on the substrate. The first metal layer includes a first light-shielding part. By connecting the first light-shielding part to a constant voltage source, a potential of the first light-shielding part is ensured to be always in a stable state, preventing the potential of the first light-shielding part from floating, and then avoiding an electrical noise problem caused by a floating potential of the first light-shielding part.

Abstract: The present disclosure provides a semiconductor device and a display panel, the semiconductor device includes an insulating substrate, at least one data input terminal, and a plurality of clock lines. By dividing a plurality of shift registers into a plurality of shift register groups, each clock line of the plurality of clock lines controls a rate of a shift register group, and compared with the case of controlling all of the shift registers through a single clock line, a rate of the shift register may be easily increased to a higher value as frequencies of a plurality of clock signals increase.

Abstract: An array substrate and a display panel are provided by the present disclosure. A light-shielding electrode of the array substrate is located outside pixel opening regions. The light-shielding electrode is configured to cooperate with a common electrode and form at least some slits. The common electrode includes a plurality of first electrode lines arranged at a different layer from the light-shielding electrode. At least one of the first electrode lines passes through at least one of the pixel opening regions, so as to form at least two slits in the at least one of the pixel opening regions with the light-shielding electrode.

Abstract: A display system and a display device are disclosed in embodiments of the present application. The display system includes a display panel and a reflective assembly configured to receive an image source, project the image source to an eye, and form a virtual image. Data lines and scan lines in an array substrate of the display panel intersect to form opening areas, and sub-pixel openings are provided in a black matrix layer of a counter substrate of the display panel. In a top view of the display panel, a center of each of the opening areas is offset relative to a center of a corresponding one of the sub-pixel openings.

Abstract: A display panel is provided by embodiments of the present application, a thin film transistor includes: a first gate electrode including a first side slope, a second side slope oppositely arranged, and a top surface; a first gate insulating layer covering the first gate electrode; a semiconductor layer arranged on the first gate insulating layer, wherein the semiconductor layer includes a first end, a second end, and a channel arranged between the first end and the second end, the second end is at least partially on the top surface, the channel is at least partially located on the first side slope.

Abstract: In an array substrate of the present invention, only two insulating layers are arranged on a planarization layer. Compared with conventional techniques that require at least four insulating layers arranged on the planarization layer, a number of the insulating layers arranged on the planarization layer is reduced. Therefore, a number of photomasks is reduced in a manufacturing process of the array substrate, and the manufacturing process is simplified. The present invention also provides a manufacturing method of the array substrate, and a display panel.

Abstract: The present disclosure provides a display panel and a mobile terminal, the display panel includes a substrate and a thin film transistor layer, the thin film transistor layer including a semiconductor layer, an insulating layer and a first metal layer, the insulating layer being disposed on the substrate and the semiconductor layer and covering the semiconductor layer, the first metal layer being disposed on the insulating layer, the insulating layer including at least one via hole, the first metal layer being connected to the semiconductor layer through the via hole, and an included angle between a sidewall of the via hole and a bottom surface of the insulating layer being greater than or equal to 85 degrees and less than or equal to 90 degrees.

Abstract: The present disclosure provides a display panel and display device. The display panel includes a substrate, a first binding layer, and a first insulating layer. A first notch is formed in an area of the first insulating layer close to a side surface, a first protrusion portion is disposed on a binding terminal and formed in the first notch, and the first protrusion portion is in contact with a first surface, thereby improving an effective conductive area of the binding area, improving the conductivity of a line, increasing the number of conductive electrons, decreasing the contact impedance, reducing the risk of abnormal binding, and improving the product yield.

Abstract: A semiconductor device and an electronic device are provided. A through hole is formed in an insulating layer and located on a first active layer. A thin-film transistor layer includes a third active layer. At least part of the third active layer is located on a sidewall of the through hole. One side of the third active layer is connected to a first active layer, and the other side of the third active layer is connected to a second active layer, so that a channel length is reduced, short channel effect is reduced, on-state current is increased, and power consumption is reduced.

Abstract: An array substrate and a display panel are provided. By allowing a gate electrode layer between a first active layer and a second active layer to overlap the first active layer and the second active layer at least partially, respectively, an area occupied by the first active layer, the second active layer, and the gate electrode layer can be reduced, and a design area of sub-pixels can be increased, thereby improving an aperture ratio.

Abstract: An embodiment of the present disclosure is directed to a display panel. The display panel includes a plurality of scan lines and a plurality of forward and reverse scan pull-down circuit. The plurality of scan lines is located on the display area. Each of the forward and reverse scan pull-down circuits includes a forward scan control module, a reverse scan control module, and a pull-down module located on a display area. The pull-down module includes an output terminal and a control terminal coupled to an output terminal of the forward scan control module and an output terminal of the reverse scan control module.

Abstract: The disclosure provides an array substrate and a display panel including the same. The array substrate includes a first cushion layer including a first side slope surface and a second side slope surface disposed opposite to each other, a first transistor including a first semiconductor layer, and a second transistor including a second semiconductor layer. A channel of the first semiconductor layer is partially located on the first side slope surface, a plane of a channel of the second semiconductor layer is parallel to a substrate, and an electron mobility of the first semiconductor layer is greater than an electron mobility of the second semiconductor layer.

Abstract: The present application provides a thin film transistor substrate and an electronic device. The thin film transistor substrate includes: a substrate; a boss including an undercut structure, the undercut structure is located on a side wall of the boss; a filler located in the undercut structure; and an active layer located on the boss and the substrate, the active layer includes a channel, and the channel covers the undercut structure and the filler.

Abstract: An array substrate and a display panel are provided. The array substrate includes an active layer. The active layer includes a channel portion and a doped portion. The doped portion includes a first doped layer and a second doped layer. The channel portion includes a first channel portion and a second channel portion. The first channel portion is connected to the first doped layer. The second channel portion is connected to the second doped layer. A part of the second channel portion overlaps with a part of the first doped layer, thus, a step-laminated structure is formed, and an overall performance of the device is improved.

Abstract: The present application provides a display panel and a display device, the display panel includes: N scan lines, the N is an integer greater than or equal to 1; and J sets of forward and reverse scan pull-down circuits, each set of the forward and reverse scan pull-down circuits includes N forward and reverse scan pull-down modules, at least a part of each of the forward and reverse scan pull-down modules is disposed in the display subarea, and the J is an integer greater than or equal to 1. In each set of the forward and reverse scan pull-down circuits, output terminals of the N forward and reverse scan pull-down modules are connected to the N scan lines in a one-to-one correspondence.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes a plurality of scan lines and at least one pull-down circuit unit. The pull-down circuit includes a forward scan pull-down unit and/or a reverse scan pull-down unit. The forward scan pull-down unit receives a (n+m)th scan signal, a first control signal, and a reference low level signal, and is connected to the nth scan line. The reverse scan pull-down unit receives a (n?m)th scan signal, a second control signal, and the reference low level signal, and is connected to the nth scan line.

Abstract: A display panel includes an active area and an irregular-shaped area. The display panel includes one or more first signal lines, one or more second signal lines, and a compensation circuit. The length of the first signal line is greater than that of the second signal line. The compensation circuit includes one or more compensation modules, the one or more compensation modules including compensation units arranged at intervals, and at least one of the compensation units being connected to a respective one of the second signal lines. Each of the one or more compensation modules further includes one or more control signal lines, and each of the one or more control signal lines is configured to control connectivity between one of the compensation units and a respective one of the second signal lines.