Abstract: The present application provides a display panel in which transistors in an input pull-up module, a stage transfer output module, and an output pull-up module are provided as P-type low temperature polysilicon thin film transistors, and a transistor in an output pull-down module is provided as an N-type metal oxide thin film transistor.

Abstract: A display panel and a manufacturing method thereof, and a display device are provided. The display panel includes a backlight module and an array substrate. The array substrate includes an insulation structure is located in the opening region. A first groove is defined at a side of the insulation structure away from the backlight module. A first insulation layer and a second insulation layer are filled in the first groove. The second insulation layer is located on a side of the first insulation layer close to the backlight module, and a refractive index of the second insulation layer is less than a refractive index of the first insulation layer.

Abstract: An array substrate, a display panel, and an electronic device are provided. The array substrate includes a substrate, a first conductive layer including a first connection part, a fourth insulating layer disposed on the first conductive layer and provided with a second via, and a second conductive layer disposed on the fourth insulating layer and in the second via. The second conductive layer includes a second electrode, and the second electrode is connected to the first connection part through the second via.

Abstract: Disclosed are a method and system for setting options of a basic input output system (BIOS), a device and a storage medium. The method includes: numbering different option combination modes; creating a first combination structure of the options configured to store numbers of the different option combination modes; sending a default option combination mode value from the BIOS to a baseboard management controller, and forming a second combination structure in the baseboard management controller; and reading configure values from the second combination structure, and executing different operations for option setting according to different configure values. According to the method, the options occupy a small storage space of the baseboard management controller, such that cost of a memory is saved. Logical processing is carried out by means of flag bits, such that the options are synchronized and set between the different combination modes.

Abstract: A gate driving circuit and a display panel are disclosed. A pull-up control module and a pull-down module of each stage gate driving unit are connected to a first node. A thin film transistor in the pull-up control module and/or pull-down module that is connected to the first node is an oxide thin film transistor, such that a leakage current of the first node is reduced due to the advantage of the small off-state leakage current of the oxide thin film transistor. Therefore, the voltage level of the first node can remain stable during a pull-up stage and a touch suspension stage.

Abstract: A semiconductor device and a display panel are disclosed. The semiconductor device includes an insulating substrate and a thin film transistor on the insulating substrate. The thin film transistor includes a protrusion and an active layer. The protrusion includes a first sub-protrusion on the insulating substrate, and a second sub-protrusion on the first sub-protrusion. The second sub-protrusion completely covers a side of the first sub-protrusion away from the insulating substrate. The active layer includes a first ohmic contact portion, a channel portion connected to the first ohmic contact portion, and a second ohmic contact portion connected to the channel portion. The first ohmic contact portion is at least partially disposed on the insulating substrate. The channel portion is fitted to a side surface of the first sub-protrusion and a side surface of the second sub-protrusion.

Abstract: A synthesis and an application of a phosphatase degrader are provided. The phosphatase degrader is a compound represented by formula I, or a salt thereof, or a deuterated compound thereof, or a stereoisomer thereof, or a solvate thereof, or a hydrate thereof, or a prodrug thereof. The compound can be used as a phosphatase degrader, especially as an SHP2 protein degrader, can treat malignant diseases such as tumors, and has good application prospects.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes a thin film transistor; and further includes a substrate; a first metal layer disposed on the substrate and including a gate of the thin film transistor; an active layer disposed on a side of the first metal layer away from the substrate and including an active portion of the thin film transistor; a spacer layer disposed on a side of the active layer away from the first metal layer and including a plurality of contact holes; a second metal layer disposed on a side of the spacer layer away from the active layer and including a source and a drain of the thin film transistor; an orthographic projection of the gate electrode on the substrate covers an orthographic projection of at least part of the contact holes on the substrate.

Abstract: A method and apparatus for optimally configuring a capacity of a high-proportion new energy system, a device, and a medium, which belong to the field of new energy system optimization and are used for solving the problems of insufficient flexibility of the high-proportion new energy system during the heating period and difficult consumption of renewable energy. The method includes: constructing a high-proportion new energy system structure; establishing a concentrating solar power (CSP) unit model and a combined heat and power (CHP) unit model based on the proposed structure; establishing a high-proportion new energy system collaborative optimization model based on the proposed unit models; acquiring relevant data of various units and renewable resource data; and obtaining a capacity configuration and operation optimization scheme of various units in the high-proportion new energy system according to the established model, thereby improving the renewable energy consumption of the system.

Abstract: Embodiments of the present disclosure disclose a driving substrate, a display panel, and a manufacturing method of the driving substrate. In the driving substrate, a first electrode is connected to a first thin film transistor; a photosensitive diode includes a first semiconductor layer and an intrinsic semiconductor layer sequentially disposed on the first electrode, the intrinsic semiconductor layer wraps the first semiconductor layer and the first electrode; and a second conductive layer is disposed on the photosensitive diode. The second conductive layer includes a second electrode, and the second electrode covers the photosensitive diode.

Abstract: The present application provides a display panel and a display device. An N-th auxiliary unit is arranged in a display area of the display panel. An output end of the N-th auxiliary unit is connected to an N-th scan line. By connecting the auxiliary unit arranged in the display area to the corresponding scan line, a falling edge of a scan signal transmitted in the scan line can have sharp falling or a rising edge of the scan signal can have sharp rising, which can alleviate a signal distortion problem caused by transmission delay in the display area.

Abstract: A display panel is provided by embodiments of the present application, a thin film transistor includes: a first gate electrode including a first side slope, a second side slope oppositely arranged, and a top surface; a first gate insulating layer covering the first gate electrode; a semiconductor layer arranged on the first gate insulating layer, wherein the semiconductor layer includes a first end, a second end, and a channel arranged between the first end and the second end, the second end is at least partially on the top surface, the channel is at least partially located on the first side slope.

Abstract: A display panel and a display device are provided. The display panel includes: an active layer, a gate, and a gate auxiliary structure. The active layer is disposed along a first direction and includes a channel layer. The gate is disposed above the channel layer and a width of the gate along the first direction is equal to a length of the channel layer along the first direction. The gate auxiliary structure is disposed adjacent to the gate. The width of the gate along the first direction is less than 1 micrometer.

Abstract: A display panel and a display device are provided. Waveform adjustment modules with a higher distribution density are arranged in an area of a display area farther away from a gate driving circuit. This way, a problem of significant delays of scan signals in the display panel is improved, and the scan signals have the same or similar delays at different positions of the display area, which is advantageous for improving the display uniformity.

Abstract: The present application discloses a gate driving circuit and a display panel. The gate driving circuit comprises a plurality of cascaded gate driving modules. A first driving signal can be output through a first output node, and at the same time, a second driving signal with a same phase as the first driving signal can be output through a second output node, and a gate driving sub-module and an in-phase output sub-module share the first output node and a pull-down node, which simplifies a circuit topology of the gate driving circuit.

Abstract: Methods, systems, and devices related to related to digital wireless communication, and more specifically, to techniques related to maintaining a serving cell state. In one exemplary aspect, a method for wireless communication includes detecting an occurrence of an event. The method also includes modifying the state configuration of the serving cell based on the occurrence of the event.

Abstract: A display substrate includes a substrate, scan signal lines, a plurality of first pixel circuits and a plurality of first light-emitting devices. The plurality of first pixel circuits are disposed on the substrate, and are located in a functional device setting region. At least one first pixel circuit includes a first transistor. At least one first light-emitting device includes a first electrode. The at least one first light-emitting device includes at least one first color light-emitting device, and the at least one first pixel circuit includes at least one first color pixel circuit, and a first color pixel circuit is electrically connected to a first color light-emitting device. An orthographic projection of a channel region of a first transistor in the first color pixel circuit on the substrate is at least partially overlapped with an orthographic projection of a first electrode of the first color light-emitting device on the substrate.

Abstract: The present application discloses a gate drive circuit and a display device. The gate drive circuit includes a plurality of cascaded gate drive units, in which one of the gate drive units includes a first layout, an input module and a pull-up module. By receiving a potential changeable signal by the gate of a first transistor or the gate of a second thin-film transistor, it can alleviate or avoid current leakage caused when a first node keeps at a same voltage level for a long time, thereby improving the stability of the potential of the first node.

Abstract: The disclosure provides a ventilation apparatus. The ventilation apparatus includes a housing, an inhalation branch, a control unit, a gas source port, an exhalation branch, and a paramagnetic oxygen sensor. The paramagnetic oxygen sensor is used for detecting the oxygen content in the inhalation branch. The gas source port is disposed on the housing. The inhalation branch, the control unit, and the exhalation branch are enclosed within the housing. The paramagnetic oxygen sensor is disposed outside the housing.

Abstract: An array substrate includes a substrate, a first metal layer and an active layer disposed on the substrate, an interlayer insulating layer, and a second metal layer. The first metal layer forms at least one first trace, the interlayer insulating layer is disposed on the first metal layer and the active layer, the second metal layer is disposed on the interlayer insulating layer, the interlayer insulating layer is formed with a first contact hole, and the second metal layer is connected to the first trace through the first contact hole. The first metal layer includes a conductive layer and a first protective layer stacked in sequence.