Patents by Inventor FEI AN

FEI AN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12001518
    Abstract: A method for predicting matching degree between a resume and a post, and a related device are provided in this disclosure. In the method for predicting the matching degree between the resume and the post, and the related device according to this disclosure, firstly the semi-structured keys and values in post information and resume information and their source are obtained. Then, the matching degree between the resume information and the post information is predicted by a prediction model including a cascaded pre-trained language model, a Transformer encoder and a single label classification model, based on the keys and values of a respective post information and resume information attribute, and corresponding source representations. Thus, by comprehensively searching internal interaction and external interaction of semi-structured multivariate attributes in person-post matching, the matching result is more accurate.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: June 4, 2024
    Assignee: National University of Defense Technology
    Inventors: Honghui Chen, Taihua Shao, Chengyu Song, Miao Jiang, Mengru Wang, Xin Zhang, Fei Cai, Dengfeng Liu, Siyuan Wang
  • Patent number: 12004113
    Abstract: A method for processing a Non-access stratum request and network devices are provided. The method includes: receiving the NAS request of a terminal device and at least two tracking area identities for the terminal device from a second network device and accepting the NAS request.
    Type: Grant
    Filed: August 30, 2023
    Date of Patent: June 4, 2024
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Jingran Chen, Fei Lu, Haitao Li
  • Patent number: 12002248
    Abstract: The present application is applicable to the field of image processing, and provides an image splicing method and apparatus, a computer-readable storage medium, a computer device, and cameras.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: June 4, 2024
    Assignee: ARASHI VISION INC.
    Inventors: Tan Su, Fei Gao
  • Patent number: 12002877
    Abstract: Field effect transistors (FET) including quantum layers. A FET may include a substrate, and an oxide layer disposed over the substrate. The oxide layer may include a first section and a second section positioned adjacent the first section. The FET may also include a first quantum layer disposed over the first section of the oxide layer, and a second quantum layer disposed over the second section of the oxide layer, and a first segment of the first quantum layer. Additionally, the FET may include a drain region disposed directly over a second segment the first quantum layer. The second segment of the first quantum layer may be positioned adjacent the first segment of the first quantum layer. The FET may further include a source region disposed over the second quantum layer, and a channel region formed over the second quantum layer, between the drain region and the source region.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: June 4, 2024
    Assignee: The Research Foundation for the State University of New York
    Inventors: Huamin Li, Fei Yao
  • Patent number: 12002685
    Abstract: Disclosed is a method for packaging a chip, comprising the following steps: providing a baseplate formed with an open slot thereon penetrating through opposite sides of the baseplate; providing a release base material, wherein the release base material is bonded to a first side of the baseplate and covers the open slot; providing a chip, wherein the chip is mounted on the release base material at the position of the open slot; packaging a second side of the baseplate facing away from the release base material so as to form a packaging layer which packages the chip and fixes it on the baseplate; removing the release base material so as to obtain a package structure for the chip.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: June 4, 2024
    Assignee: Weifang Goertek Microelectronics Co., Ltd.
    Inventors: Baoguan Yin, Fei She, Dewen Tian, Qinglin Song
  • Patent number: 11998016
    Abstract: The present disclosure provides use of a Chaetomium globosum strain in controlling Fusarium crown rot (FCR) of wheat. The C. globosum strain under the deposit designation of 12XP1-2-3 is deposited at China General Microbiological Culture Collection Center (CGMCC) on Jan. 23, 2019 with an accession number of CGMCC No. 17183. Field experiments conclude that coating of wheat seeds with Chaetomium globosum strain 12XP1-2-3 can reduce diseased stem rate, disease rating, and disease index by 19.0%-41.3%, 43.7%, and 4.7%-45.4%, respectively.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: June 4, 2024
    Assignee: Institute of Plant Protection, Henan Academy of Agricultural Sciences
    Inventors: Fei Xu, Yuli Song, Junmei Wang, Jiaojiao Zhang, Zixing Han, Yahong Li, Ruijie Shi, Lijuan Li, Lulu Liu
  • Patent number: 12002549
    Abstract: The present invention provides a knowledge reuse-based method and system for predicting a cell concentration in a fermentation process. The method includes: constructing a cell concentration soft sensor universal model in a fermentation process; acquiring and preprocessing process data of a fermentation stage A; determining a cell concentration soft sensor model of the fermentation stage A; designing a cell concentration online soft sensor of a fermentation stage B; and predicting a cell concentration of the fermentation stage B according to the cell concentration online soft sensor of the fermentation stage B. The present invention resolves the problems of weak generalization of a cell concentration soft sensor model and high costs of establishing models for fermentation stages separately, thereby improving the prediction accuracy of a cell concentration soft sensor.
    Type: Grant
    Filed: July 11, 2023
    Date of Patent: June 4, 2024
    Assignee: JIANGNAN UNIVERSITY
    Inventors: Xiaoli Luan, Xiaojing Ping, Haiying Wan, Fei Liu
  • Publication number: 20240176116
    Abstract: An optical lens assembly includes: a first element group including: a first lens group with positive refractive power, including one or two lenses; a second element group including: a second lens group with positive refractive power, including two or three lenses; an optical element including, in order from a visual side to an image source side: an absorptive polarizer, a reflective polarizer and a first phase retarder; and a partial-reflective-partial-transmissive element; and a third element group including an image source plane. The first element group, the second element group and the third element group are arranged in order from the visual side to the image source side. When the optical lens assembly satisfies a specific condition, the weight of the device can be reduced, the zoom function can be provided, and the image quality can be ensured.
    Type: Application
    Filed: February 17, 2023
    Publication date: May 30, 2024
    Inventors: Ping-Yi CHEN, Fei-Hsin TSAI, Cong GE
  • Publication number: 20240179164
    Abstract: Detection of strategically aged domains is detected. A list of aged dormant domains is determined, including by evaluating passive Domain Name System (DNS) information. The list of aged dormant domains is monitored for a change by an aged dormant domain from a dormant domain status to an active status. In response to determining the change to active status of the aged dormant domain, an action is taken with respect to the aged dormant domain.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Inventors: Zhanhao Chen, Daiping Liu, Wanjin Li, Fan Fei
  • Publication number: 20240178777
    Abstract: A method for pre-positioning a rotor of an outdoor fan in a counter-rotation state before operation includes: 1) during a counter-operation state, sending, by a microprocessor, a signal to the inverter circuit to turn off all upper electronic switching tubes and turn on all lower electronic switching tubes; 2) measuring a phase current of each phase coil winding in the stator assembly; 3) calculating a back electromotive force of each phase coil winding in the stator; 4) calculating a position angle of the rotor assembly; 5) checking if the phase current of each phase coil winding is all smaller than a preset threshold current; if not, return to 1); if yes, proceed to 6); and 6) calculating a resistance torque to stop the rotor assembly based on the position angle of the rotor assembly, and then stopping the rotor assembly to achieve pre-positioning of the rotor before starting.
    Type: Application
    Filed: July 13, 2023
    Publication date: May 30, 2024
    Inventors: Fei YANG, Min WANG, Song LUO, Chao LI
  • Publication number: 20240179610
    Abstract: This application provides an IAB network includes a first BAP topology and a second BAP topology, the first BAP topology is managed by a first donor node, the second BAP topology is managed by a second donor node. In the IAB network, a first IAB node receives a first data packet, where the first IAB node is managed by the first donor node, at least one parent node of the first LAB node is managed by the second donor node, and the first IAB node belongs to the first BAP topology. The first IAB node processes the first data packet based on a BAP topology corresponding to an ingress link for receiving the first data packet.
    Type: Application
    Filed: February 2, 2024
    Publication date: May 30, 2024
    Inventors: Fei Sun, Kuikui Li, Yuanping Zhu, Yulong Shi
  • Publication number: 20240178160
    Abstract: A package structure and an electronic apparatus includes a power semiconductor device, a wire, and a shape memory object. The wire is electrically connected to the power semiconductor device, the shape memory object is in contact with the wire, and the shape memory object is configured to deform when temperature of the shape memory object is not less than preset temperature, to enable a current in the wire to be cut off or reduced. In this way, impact of high temperature generated by the power semiconductor device when an overcurrent occurs in the power semiconductor device on the printed circuit board is reduced, a possibility that a printed circuit board is damaged is greatly reduced, and an overcurrent self-protection capability of the package structure is implemented.
    Type: Application
    Filed: February 9, 2024
    Publication date: May 30, 2024
    Inventors: Ming WU, Zhiqiang XIANG, Fei DING, Qidong WANG
  • Publication number: 20240176539
    Abstract: This application describes systems and methods for facilitating memory access in flash drives. An example method performed by a memory controller may include receiving, from a host, a write command comprising data to be written into a flash memory; splitting the data into a first portion and a second portion; storing the first portion into a static random-access memory (SRAM) in the memory controller; storing the second portion into a dynamic random-access memory (DRAM) communicatively coupled with the memory controller; initiating a configuration operation corresponding to the write command; fetching the first portion from the SRAM and the second portion from the DRAM in response to the flash translation layer indicating a ready status to store the data into the flash memory; combining the fetched first portion and the fetched second portion; and storing the combined first portion and the second portion into the flash memory.
    Type: Application
    Filed: February 24, 2023
    Publication date: May 30, 2024
    Inventors: Jifeng WANG, Yuming XU, Wentao WU, Fei XUE, Xiang GAO, Jiajing JIN
  • Publication number: 20240178668
    Abstract: An inverter and a control method for the inverter. The inverter includes a direct current conversion circuit, a direct current bus, an inverter circuit, and a controller. An input end of the direct current conversion circuit is connected to an input end of the inverter, an output end of the direct current conversion circuit is connected to an input end of the inverter circuit through the direct current bus, and an output end of the inverter circuit is connected to an output end of the inverter. The controller obtains a reactive voltage control amount based on actual output active power and reference output active power of the inverter circuit and adjusts an output voltage of the inverter circuit based on the reactive voltage control amount and a reference output voltage.
    Type: Application
    Filed: November 29, 2023
    Publication date: May 30, 2024
    Applicant: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Fei XU, Xinyu YU, Mingquan ZHAO, Zisen QU, Kai XIN
  • Publication number: 20240174995
    Abstract: The invention relates to the field of genetic engineering. In particular, the present invention relates to a genome editing system and method based on C2c1 nuclease.
    Type: Application
    Filed: November 30, 2018
    Publication date: May 30, 2024
    Applicant: Institute of Zoology, Chinese Academy of Sciences
    Inventors: Wei Li, Qi Zhou, Fei Teng
  • Publication number: 20240172870
    Abstract: Disclosed are a self-locking folding bracket and a folding chair. The self-locking folding bracket includes two symmetrical foldable side supporting structures and a linkage assembly connected between the two side supporting structures, the linkage assembly includes two groups of side rods, two groups of cross rods and two groups of connecting rods, the cross rod and the connecting rod have an extreme position in the rotation process, the linkage assembly has a working state that passes down the extreme position so that the cross rod is abutted to the side rod, a folding state that the cross rod passes up the extreme position to leave the side rod, when the linkage assembly is in the working state, the linkage assembly is unfolded and able to maintain a distance between the two side supporting structures.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Applicant: Yongkang Mantuo Import & Export Co., Ltd
    Inventors: Fei YAO, Meiju YING
  • Publication number: 20240179760
    Abstract: Disclosed are a synchronization mechanism and a foldable terminal. In the synchronization mechanism, a first rotating component and a second rotating component are in transmission connection by using a first worm, a worm gear, and a second worm that are sequentially meshed, thereby implementing the synchronous rotation of the first rotating component and the second rotating component relative to a base. In addition, when the synchronization mechanism is applied to the foldable terminal, since an axial direction of the worm gear and a radial direction of the first worm and the second worm are consistent with a thickness direction of the body, and an axial size of the worm gear and radial sizes of the first worm and the second worm are relatively small, which is conducive to the light and thin design of the foldable terminal.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 30, 2024
    Applicant: Honor Device Co., Ltd.
    Inventors: Zhen ZHANG, Fei CEN, Yongbao YUE, Xiaolong REN
  • Publication number: 20240178978
    Abstract: Methods and systems for techniques for determining transmission configuration indicator (TCI) states are disclosed. In an implementation, a method of wireless communication includes receiving, by a wireless device, at least one of a first transmission configuration indicator (TCI) state for a first direction transmission or a second TCI state for a second direction transmission, determining, by the wireless device, an indicated TCI state based on the first TCI state for a certain second direction transmission, and performing, by the wireless device, the certain second direction transmission according to the indicated TCI state.
    Type: Application
    Filed: December 7, 2023
    Publication date: May 30, 2024
    Inventors: Ke YAO, Shujuan ZHANG, Bo GAO, Chenchen ZHANG, Fei DONG
  • Publication number: 20240179897
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer, a continuous charge storage material layer vertically extending through a plurality of the electrically conductive layers, a vertical stack of discrete charge storage elements located at levels of the electrically conductive layers and contacting a respective surface segment of an outer sidewall of the continuous charge storage material layer, and a vertical stack of discrete blocking dielectric material portions containing silicon atoms and oxygen atoms and located at the levels of the electrically conductive layers and vertically spaced apart from each other.
    Type: Application
    Filed: July 12, 2023
    Publication date: May 30, 2024
    Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Adarsh RAJASHEKHAR, Fei ZHOU
  • Publication number: 20240178753
    Abstract: The present invention discloses a regulator. The regulator includes a bias voltage generating circuit and a flipped voltage follower (FVF), wherein the bias voltage generating circuit is configured to generate a bias voltage, and the FVF is configured to generate an output voltage according to the bias voltage and a supply voltage. The FVF includes a first P-type transistor and a first N-type transistor. The P-type transistor is configured to receive the bias voltage via a gate electrode of the P-type transistor, to generate the output voltage on a source electrode of the P-type transistor. A drain electrode of the first N-type transistor is connected to the supply voltage, a source electrode of the first N-type transistor is connected to the source electrode of the first P-type transistor, and a gate electrode of the first N-type transistor receives a driving signal for compensating the output voltage.
    Type: Application
    Filed: April 16, 2023
    Publication date: May 30, 2024
    Applicant: Faraday Technology Corp.
    Inventors: Chen-Hui Xu, Xiao-Dong Fei, Wen-Chi Huang, Hui-Wen Hu