Abstract: A method and apparatus for positioning one component relative to another component. First metrology data may be identified for a first component and second metrology data may be identified for a second component. First locations of first features may be identified on the first component using the first metrology data. Second locations of second features on the second component may be identified using the second metrology data. A transformation may be computed based on the first locations identified and the second locations identified for use in modifying a movement plan of a robotic system for positioning the second component relative to the first component.

Abstract: An electronic device opened by magnetic force includes a bottom cover, a top cover, at least one engaging module, a conductive logo, and at least one electromagnet. The top cover is capable of being opened and closed relative to the bottom cover. The top cover has a first engaging portion. The engaging module is disposed at the bottom cover and has a magnetic attraction portion, an elastic element and a second engaging portion. When the conductive logo is electrified, the electromagnet generates magnetism for attracting the magnetic attraction portion to drive the second engaging portion to be separated from the first engaging portion thus deforming the elastic element to allow the top cover to be opened. When the conductive logo is stopped from being electrified, the elastic element is restored to allow the second engaging portion to return to the original position.

Abstract: Techniques for utilizing two or more mobile devices equipped with projectors to generate a combined seamless user interfaces by stitching projection areas generated by the projectors.

Abstract: Computing devices are often designed in view of a particular usage scenario, but may be unsuitable for usage in other computing scenarios. For example, a notebook computer with a large display, an integrated keyboard, and a high-performance processor suitable for many computing tasks may be heavy, large, and power-inefficient; and a tablet lacking a keyboard and incorporating a low-powered processor may improve portability but may present inadequate performance for many tasks. Presented herein is a configuration of a computing device featuring a display unit with a resource-conserving processor that may be used independently (e.g., as a tablet), but that may be connected to a base unit featuring a resource-intensive processor. The operating system of the device may accordingly transition between a resource-intensive computing environment and a resource-conserving computing environment based on the connection with the base unit, thereby satisfying the dual roles of workstation and portable tablet device.

Abstract: An electronic device opened by magnetic force includes a bottom cover, a top cover, at least one engaging module, a conductive logo, and at least one electromagnet. The top cover is capable of being opened and closed relative to the bottom cover. The top cover has a first engaging portion. The engaging module is disposed at the bottom cover and has a magnetic attraction portion, an elastic element and a second engaging portion. When the conductive logo is electrified, the electromagnet generates magnetism for attracting the magnetic attraction portion to drive the second engaging portion to be separated from the first engaging portion thus deforming the elastic element to allow the top cover to be opened. When the conductive logo is stopped from being electrified, the elastic element is restored to allow the second engaging portion to return to the original position.

Abstract: Accelerator systems and methods are disclosed that utilize FPGA technology to achieve better parallelism and flexibility. The accelerator system may be used to implement a relevance-ranking algorithm, such as RankBoost, for a training process. The algorithm and related data structures may be organized to enable streaming data access and, thus, increase the training speed. The data may be compressed to enable the system and method to be operable with larger data sets. At least a portion of the approximated RankBoost algorithm may be implemented as a single instruction multiple data streams (SIMD) architecture with multiple processing engines (PEs) in the FPGA. Thus, large data sets can be loaded on memories associated with an FPGA to increase the speed of the relevance ranking algorithm.

Abstract: A method using a RankBoost-based algorithm to automatically select features for further ranking model training is provided. The method reiteratively applies a set of ranking candidates to a training data set comprising a plurality of ranking objects having a known pairwise ranking order. Each round of iteration applies a weight distribution of ranking object pairs, yields a ranking result by each ranking candidate, identifies a favored ranking candidate for the round based on the ranking results, and updates the weight distribution to be used in next iteration round by increasing weights of ranking object pairs that are poorly ranked by the favored ranking candidate. The method then infers a target feature set from the favored ranking candidates identified in the iterations.

Abstract: Accelerator systems and methods are disclosed that utilize FPGA technology to achieve better parallelism and flexibility. The accelerator system may be used to implement a relevance-ranking algorithm, such as RankBoost, for a training process. The algorithm and related data structures may be organized to enable streaming data access and, thus, increase the training speed. The data may be compressed to enable the system and method to be operable with larger data sets. At least a portion of the approximated RankBoost algorithm may be implemented as a single instruction multiple data streams (SIMD) architecture with multiple processing engines (PEs) in the FPGA. Thus, large data sets can be loaded on memories associated with an FPGA to increase the speed of the relevance ranking algorithm.

Abstract: Accelerator systems and methods are disclosed that utilize FPGA technology to achieve better parallelism and processing speed. A Field Programmable Gate Array (FPGA) is configured to have a hardware logic performing computations associated with a neural network training algorithm, especially a Web relevance ranking algorithm such as LambaRank. The training data is first processed and organized by a host computing device, and then streamed to the FPGA for direct access by the FPGA to perform high-bandwidth computation with increased training speed. Thus, large data sets such as that related to Web relevance ranking can be processed. The FPGA may include a processing element performing computations of a hidden layer of the neural network training algorithm. Parallel computing may be realized using a single instruction multiple data streams (SIMD) architecture with multiple arithmetic logic units in the FPGA.

Abstract: Accelerator systems and methods are disclosed that utilize FPGA technology to achieve better parallelism and flexibility. The accelerator system may be used to implement a relevance-ranking algorithm, such as RankBoost, for a training process. The algorithm and related data structures may be organized to enable streaming data access and, thus, increase the training speed. The data may be compressed to enable the system and method to be operable with larger data sets. At least a portion of the approximated RankBoost algorithm may be implemented as a single instruction multiple data streams (SIMD) architecture with multiple processing engines (PEs) in the FPGA. Thus, large data sets can be loaded on memories associated with an FPGA to increase the speed of the relevance ranking algorithm.

Abstract: Techniques for utilizing two or more mobile devices equipped with projectors to generate a combined seamless user interfaces by stitching projection areas generated by the projectors.

Abstract: A method using a RankBoost-based algorithm to automatically select features for further ranking model training is provided. The method reiteratively applies a set of ranking candidates to a training data set comprising a plurality of ranking objects having a known pairwise ranking order. Each round of iteration applies a weight distribution of ranking object pairs, yields a ranking result by each ranking candidate, identifies a favored ranking candidate for the round based on the ranking results, and updates the weight distribution to be used in next iteration round by increasing weights of ranking object pairs that are poorly ranked by the favored ranking candidate. The method then infers a target feature set from the favored ranking candidates identified in the iterations.

Abstract: Accelerator systems and methods are disclosed that utilize FPGA technology to achieve better parallelism and processing speed. A Field Programmable Gate Array (FPGA) is configured to have a hardware logic performing computations associated with a neural network training algorithm, especially a Web relevance ranking algorithm such as LambaRank. The training data is first processed and organized by a host computing device, and then streamed to the FPGA for direct access by the FPGA to perform high-bandwidth computation with increased training speed. Thus, large data sets such as that related to Web relevance ranking can be processed. The FPGA may include a processing element performing computations of a hidden layer of the neural network training algorithm. Parallel computing may be realized using a single instruction multiple data streams (SIMD) architecture with multiple arithmetic logic units in the FPGA.

Abstract: A plasma ignition burner. The plasma ignition burner has at least two stages of burner barrels and a plasma generator for igniting the pulverized coal in a first stage burner barrel of the at least two stages of burner barrels. The burning flame of the former stage burner barrel ignites the pulverized coal in the next stage burner barrel, or further burns with the supplemented air in the next stage burner barrel. The axial direction of said plasma generator is parallel to the direction along which the pulverized-coal-contained air flow enters into the first stage burner barrel and at the same time, parallel to the axis of the burner barrels.

Abstract: Accelerator systems and methods are disclosed that utilize FPGA technology to achieve better parallelism and flexibility. The accelerator system may be used to implement a relevance-ranking algorithm, such as RankBoost, for a training process. The algorithm and related data structures may be organized to enable streaming data access and, thus, increase the training speed. The data may be compressed to enable the system and method to be operable with larger data sets. At least a portion of the approximated RankBoost algorithm may be implemented as a single instruction multiple data streams (SIMD) architecture with multiple processing engines (PEs) in the FPGA. Thus, large data sets can be loaded on memories associated with an FPGA to increase the speed of the relevance ranking algorithm.