Patents by Inventor Fei-Chieh Yang

Fei-Chieh Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for assembling a wafer level test probe card
    Patent number: 8146245
    Abstract: A method for assembling a probe card for wafer level testing of a plurality of semiconductor devices simultaneously is disclosed. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The method includes aligning and assembling the foregoing components, and curing the underfill. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: April 3, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Clinton Chih-Chieh Chao, Fei-Chieh Yang, Chun-Hsing Chen, Mill-Jer Wang, Sheng-Hsi Huang, Ming-Cheng Hsu
  • WAFER LEVEL TEST PROBE CARD
    Publication number: 20100229383
    Abstract: A probe card for wafer level testing of a plurality of semiconductor devices simultaneously. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing.
    Type: Application
    Filed: May 26, 2010
    Publication date: September 16, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Clinton Chih-Chieh Chao, Fei-Chieh Yang, Chun-Hsing Chen, Mill-Jer Wang, Sheng-Hsi Huang, Ming-Cheng Hsu
  • Wafer level test probe card
    Patent number: 7750651
    Abstract: A probe card for wafer level testing of a plurality of semiconductor devices simultaneously. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: July 6, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Clinton Chih-Chieh Chao, Fei-Chieh Yang, Chun-Hsing Chen, Mill-Jer Wang, Sheng-Hsi Huang, Ming-Cheng Hsu
  • WAFER LEVEL TEST PROBE CARD
    Publication number: 20090224780
    Abstract: A probe card for wafer level testing of a plurality of semiconductor devices simultaneously. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing.
    Type: Application
    Filed: June 3, 2008
    Publication date: September 10, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Clinton Chih-Chieh Chao, Fei-Chieh Yang, Chun-Hsing Chen, Mill-Jer Wang, Sheng-Hsi Huang, Ming-Cheng Hsu