Patents by Inventor Fei Fan DUAN

Fei Fan DUAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250194258
    Abstract: A filler cell region (in a semiconductor device) includes: filler-gate segments; for which a majority of first ends substantially align with a first reference line and a majority of second ends substantially align with a second reference line, the first and second reference lines being parallel and proximal to a top and bottom boundaries of the filler cell region; first and second filler-gate segments extending continuously across the filler cell region; and third & fourth and fifth & sixth filler-gate segments being correspondingly coaxial and separated by corresponding gate-gaps located centrally in the filler cell region; the first and second filler-gate segments being between the third & fourth filler-gate segments and the fifth & sixth filler-gate segments; and a first end of the first or second filler-gate segment extending to the top boundary; and a second end of the first or second filler-gate segment extending to the bottom boundary.
    Type: Application
    Filed: February 24, 2025
    Publication date: June 12, 2025
    Inventors: Shun Li CHEN, Fei Fan DUAN, Ting Yu CHEN
  • Patent number: 12237321
    Abstract: A filler cell region (in a semiconductor device) includes: gate segments, a majority of first ends of which substantially align with a first reference line that parallel and proximal to a top boundary of the filler cell region, and a majority of second ends of which substantially align with a second reference line that is parallel and proximal to a bottom boundary of the filler cell region. First and second gate segments extend continuously across the filler cell region; and third & fourth and fifth & sixth gate segments are correspondingly coaxial and separated by corresponding gate-gaps. Relative to the first direction: a first end of the first gate segment extends to the top boundary of the filler cell region; and a second end of the second gate segment extends to the bottom boundary of the filler cell region.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shun Li Chen, Fei Fan Duan, Ting Yu Chen
  • Publication number: 20240096800
    Abstract: A semiconductor device includes first and second active regions extending in parallel in a substrate, a plurality of conductive patterns, each conductive pattern of the plurality of conductive patterns extending on the substrate across each of the first and second active regions, and a plurality of metal lines, each metal line of the plurality of metal lines overlying and extending across each of the first and second active regions. Each conductive pattern of the plurality of conductive patterns is electrically connected in parallel with each metal line of the plurality of metal lines.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Fei Fan DUAN, Fong-yuan CHANG, Chi-Yu LU, Po-Hsiang HUANG, Chih-Liang CHEN
  • Patent number: 11854973
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first conductive pattern on a substrate, a second conductive pattern above the first conductive pattern, and a third conductive pattern above the first conductive pattern, all extending along a first direction. The first conductive pattern is electrically connected in parallel to the second conductive pattern and the third conductive pattern.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fei Fan Duan, Fong-yuan Chang, Chi-Yu Lu, Po-Hsiang Huang, Chih-Liang Chen
  • Publication number: 20230394217
    Abstract: Methods and Apparatuses for making an integrated circuit (IC) are disclosed. In accordance with some embodiments, a method including forming one or more decoupling capacitor (DCAP) cells comprising one or more polysilicon (PO) layers openings formed based on one or more photoresist layer openings formed to solve one or more design rule check (DRC) violations. The one or more DCAP cells also provide decoupling capacitors for the IC.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 7, 2023
    Inventors: Fei Fan DUAN, Li-Chun TIEN, Chih-Liang CHEN
  • Publication number: 20230260985
    Abstract: A filler cell region (in a semiconductor device) includes: gate segments, a majority of first ends of which substantially align with a first reference line that parallel and proximal to a top boundary of the filler cell region, and a majority of second ends of which substantially align with a second reference line that is parallel and proximal to a bottom boundary of the filler cell region. First and second gate segments extend continuously across the filler cell region; and third & fourth and fifth & sixth gate segments are correspondingly coaxial and separated by corresponding gate-gaps. Relative to the first direction: a first end of the first gate segment extends to the top boundary of the filler cell region; and a second end of the second gate segment extends to the bottom boundary of the filler cell region.
    Type: Application
    Filed: June 17, 2022
    Publication date: August 17, 2023
    Inventors: Shun Li CHEN, Fei Fan DUAN, Ting Yu CHEN
  • Publication number: 20220359392
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first conductive pattern on a substrate, a second conductive pattern above the first conductive pattern, and a third conductive pattern above the first conductive pattern, all extending along a first direction. The first conductive pattern is electrically connected in parallel to the second conductive pattern and the third conductive pattern.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 10, 2022
    Inventors: Fei Fan DUAN, Fong-yuan CHANG, Chi-Yu LU, Po-Hsiang HUANG, Chih-Liang CHEN