Abstract: The invention relates to an energy management framework and method for rail transit energy storage, which relates to the energy management field of rail transit energy storage. The energy management framework comprises central-level controller, several station-level controllers, and several device-level controllers; among them, the central-level controller is wirelessly connected to all station-level controllers; a station-level controller is connected to a device-level controller by wired communication. The invention realizes the energy management of rail transit energy storage based on the above three-level energy management framework (center level, station level and device level structure).

Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

Abstract: The present invention relates to a method for producing an at least partially coated object and to an at least partially coated object obtained by the method. The method comprises bringing the object completely or partly into contact with a treating agent; leaving the object at 10° C.-30° C. and 100 mbar-800 mbar for 3-10 minutes; and heat-treating the object at a temperature of 70° C.-90° C.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes: providing a first wafer including a substrate; forming a hole in the first wafer, which extends through the substrate; forming an insulating dielectric layer over a side wall of the hole; filling the hole with a conductive layer; removing at least part of the insulating dielectric layer situated in correspondence with the substrate, forming an air gap between the conductive layer and the substrate; and forming a closure layer, which closes the air gap. With the present invention, parasitic capacitance present between the conductive layer, the insulating dielectric layer and the substrate is significantly reduced, resulting in an improvement in performance of the semiconductor device.

Abstract: The present application discloses a method and a model for controlling an energy storage system for rail transit, a device, and a storage medium. The method includes: determining an offline charging-discharging action according to a state of an energy storage system based on an offline algorithm; determining an online charging-discharging action according to the state of the energy storage system based on a deep reinforcement learning algorithm; acquiring a fusion ratio of the offline charging-discharging action to the online charging-discharging action according to a communication delay amount and a delay degree; and fusing the offline charging-discharging action and the online charging-discharging action according to the fusion ratio and outputting a fusion result to the energy storage system.

Abstract: A control method, device, apparatus and storage medium for a supercapacitor energy storage device is provided, where the method includes: collecting life characterization parameters of the supercapacitor energy storage device and performing life evaluation to obtain a life evaluation result, inputting the life evaluation result into a constructed fuzzy rule base, and outputting a constraint condition adjustment parameter; obtaining a constraint condition according to the constraint condition adjustment parameter, and optimizing control parameters using a genetic algorithm in conjunction with an optimized objective function to obtain first control parameters; and controlling charging and discharging currents of the supercapacitor energy storage device using a droop control method according to the first control parameters.

Abstract: An effective capacity estimation method and system for super capacitor energy storage systems are provided. The method includes: establishing a nonlinear electrical model of supercapacitor cell and an equivalent electrical model of a supercapacitor system; obtaining the first test data by charging the supercapacitor cell; based on the first test data, setting the initial value of parameters of the nonlinear electrical model of the supercapacitor cell by a preset algorithm; using a least-square method to identify the parameters of the nonlinear electrical model of the supercapacitor cell; obtaining electrical parameters of the equivalent electrical model of the supercapacitor system except the connection resistance parameters, carrying out a charging test of the supercapacitor system to obtain the connection resistance parameters, and estimating an effective capacity of the supercapacitor energy storage system based on the equivalent electrical model of the supercapacitor system after parameter identification.

Abstract: A phase interpolation device and a multi-phase clock generation device are provided. The phase interpolation device includes a digital controller circuit and a phase interpolator that includes a capacitor and circuit branches, which are controlled by the digital controller circuit to generate an n-th phase clock of N phase clocks between first and second input clocks. When the n-th phase clock is generated, the digital controller circuit controls, in response to appearances of rising edges of the first input clock, the circuit branches to charge the capacitor using (N?n+1)×M ones of the first current source, and controls, in response to appearances of rising edges of the second input clock, the circuit branches to use N×M ones of the first current source to charge the capacitor. N, M, n are integers.

Abstract: A slew rate control device and a slew rate control method are provided. The slew rate control device includes a signal generating circuit, a comparator circuit, and a control circuit. The signal generating circuit generates a first voltage signal and a second voltage signal having a slew rate, and the first voltage signal and the second voltage signal are a pair of differential signals. The comparator circuit outputs an enabling signal according to a relative positional relationship between an eye crossing point of the pair of differential signals and a signal edge of a reference clock. The control circuit generates at least one control signal according to the enabling signal to control the signal generating circuit, such that the signal generating circuit changes the slew rate of the first voltage signal and the second voltage signal according to the at least one control signal.

Abstract: The present invention discloses a receive data equalization apparatus. A delay-compensating calculation circuit retrieves training data groups of a training data signal to retrieve total delay amount, generate signed compensation amounts according to a relation among training data contents of training data in each of the training data groups to generate total compensation amount accordingly, and solve equations that correspond total delay amount of the training data groups to the total compensation amount to obtain each of the compensation amounts. A receive data equalization circuit receives the compensation amounts and retrieves a receive data group in a receive data signal, generate signed receive compensation amounts according to a relation among receive data contents of receive data in the receive data group to generate a total receive compensation amount accordingly to perform equalization on a terminal edge of the receive data group according to the total receive compensation amount.

Abstract: A manufacturing method of thermal paste is provided. The manufacturing method includes: providing a base material; heating a metal material to a liquid state, to generate a liquid metal material; sieving the liquid metal material to generate a metal powder material; adding a dispersant to the metal powder material and mixing to generate a mixed powder material; and mixing the mixed powder material and the base material.

Abstract: A method of measuring hematocrit is provided. The method for measuring hematocrit includes the following steps. A test strip is provided. The test strip includes a reaction region and a pair of electrodes disposed in the reaction region. A whole blood sample is entered to the reaction region. After the whole blood sample enters the reaction region, a plurality of sets of square wave voltages are intermittently applied to the pair of electrodes based on a square wave voltammetry method to obtain a plurality of feedbacks related to hematocrit. An interval between two adjacent sets of square wave voltages ranges from 0.1 seconds to 4 seconds. A feedback of an n-th set of square wave voltages is obtained to calculate a hematocrit value of the whole blood sample and n is a positive integer greater than 1. A hematocrit value is calculated according to the feedback.

Abstract: A phase interpolation device and a multi-phase clock generation device are provided. The phase interpolation device includes a digital controller circuit and a phase interpolator that includes a capacitor and circuit branches, which are controlled by the digital controller circuit to generate an n-th phase clock of N phase clocks between first and second input clocks. When the n-th phase clock is generated, the digital controller circuit controls, in response to appearances of rising edges of the first input clock, the circuit branches to charge the capacitor using (N?n+1)×M ones of the first current source, and controls, in response to appearances of rising edges of the second input clock, the circuit branches to use N×M ones of the first current source to charge the capacitor. N, M, n are integers.

Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

Abstract: A slew rate control device and a slew rate control method are provided. The slew rate control device includes a signal generating circuit, a comparator circuit, and a control circuit. The signal generating circuit generates a first voltage signal and a second voltage signal having a slew rate, and the first voltage signal and the second voltage signal are a pair of differential signals. The comparator circuit outputs an enabling signal according to a relative positional relationship between an eye crossing point of the pair of differential signals and a signal edge of a reference clock. The control circuit generates at least one control signal according to the enabling signal to control the signal generating circuit, such that the signal generating circuit changes the slew rate of the first voltage signal and the second voltage signal according to the at least one control signal.

Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes: providing a first wafer including a substrate; forming a hole in the first wafer, which extends through the substrate; forming an insulating dielectric layer over a side wall of the hole; filling the hole with a conductive layer; removing at least part of the insulating dielectric layer situated in correspondence with the substrate, forming an air gap between the conductive layer and the substrate; and forming a closure layer, which closes the air gap. With the present invention, parasitic capacitance present between the conductive layer, the insulating dielectric layer and the substrate is significantly reduced, resulting in an improvement in performance of the semiconductor device.

Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.