Patents by Inventor Fei-Lung Lai

Fei-Lung Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250243051
    Abstract: An integrated CMOS-MEMS device includes a first substrate having a CMOS device, a second substrate having a MEMS device, an insulator layer disposed between the first substrate and the second substrate, a dischargeable ground-contact, an electrical bypass structure, and a contrast stress layer. The first substrate includes a conductor that is conductively connecting to the CMOS devices. The electrical bypass structure has a conducting layer conductively connecting this conductor of the first substrate with the dischargeable ground-contact through a process-configurable electrical connection. The contrast stress layer is disposed between the insulator layer and the conducting layer of the electrical bypass structure.
    Type: Application
    Filed: April 22, 2025
    Publication date: July 31, 2025
    Inventors: Eason Hsieh, Fei-Lung Lai, Kuei-Sung Chang
  • Patent number: 12297097
    Abstract: An integrated CMOS-MEMS device includes a first substrate having a CMOS device, a second substrate having a MEMS device, an insulator layer disposed between the first substrate and the second substrate, a dischargeable ground-contact, an electrical bypass structure, and a contrast stress layer. The first substrate includes a conductor that is conductively connecting to the CMOS devices. The electrical bypass structure has a conducting layer conductively connecting this conductor of the first substrate with the dischargeable ground-contact through a process-configurable electrical connection. The contrast stress layer is disposed between the insulator layer and the conducting layer of the electrical bypass structure.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eason Hsieh, Fei-Lung Lai, Kuei-Sung Chang
  • Publication number: 20250102460
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure, an isolation layer, an interface layer in an opening of the isolation layer, and a metal crown structure over the interface layer. The interface layer and the metal crown structure are disposed on opposite side of the transistor from a gate structure.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen CHENG, Yi-Shao LIU, Fei-Lung LAI
  • Patent number: 12216077
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure, an isolation layer, an interface layer in an opening of the isolation layer, and a metal crown structure over the interface layer. The interface layer and the metal crown structure are disposed on opposite side of the transistor from a gate structure.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wen Cheng, Yi-Shao Liu, Fei-Lung Lai
  • Publication number: 20240409395
    Abstract: A semiconductor device is provided. The semiconductor device includes a metal layer. The semiconductor includes a gyroscope including a getter structure overlying the metal layer, wherein the getter structure comprises titanium.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Inventors: Chih-Chung LEE, Be-Ge Huang, Fei-Lung Lai, Chuan-Tai Wu
  • Patent number: 12151932
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Sung Chang, Chun-Wen Cheng, Fei-Lung Lai, Shing-Chyang Pan, Yuan-Chih Hsieh, Yi-Ren Wang
  • Publication number: 20230382712
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 30, 2023
    Inventors: Kuei-Sung Chang, Chun-Wen Cheng, Fei-Lung Lai, Shing-Chyang Pan, Yuan-Chih Hsieh, Yi-Ren Wang
  • Patent number: 11814283
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Sung Chang, Chun-Wen Cheng, Fei-Lung Lai, Shing-Chyang Pan, Yuan-Chih Hsieh, Yi-Ren Wang
  • Patent number: 11713242
    Abstract: In some embodiments, a sensor is provided. The sensor includes a microelectromechanical systems (MEMS) substrate disposed over an integrated chip (IC), where the IC defines a lower portion of a first cavity and a lower portion of a second cavity, and where the first cavity has a first operating pressure different than an operating pressure of the second cavity. A cap substrate is disposed over the MEMS substrate, where a first pair of sidewalls of the cap substrate partially define an upper portion of the first cavity, and a second pair of sidewalls of the cap substrate partially define an upper portion of the second cavity. A sensor area comprising a movable portion of the MEMS substrate and a dummy area comprising a fixed portion of the MEMS substrate are both disposed in the first cavity. A pressure enhancement structure is disposed in the dummy area.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Fei-Lung Lai, Kuei-Sung Chang, Shang-Ying Tsai
  • Patent number: 11703475
    Abstract: A method includes mounting an integrated electro-microfluidic probe card to a device area on a bio-sensor device wafer, wherein the electro-microfluidic probe card has a first major surface and a second major surface opposite the first major surface. The method further includes electrically connecting at least one electronic probe tip extending from the first major surface to a corresponding conductive area of the device area. The method further includes stamping a test fluid onto the device area. The method further includes measuring via the at least one electronic probe tip a first electrical property of one or more bio-FETs of the device area based on the test fluid.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Shao Liu, Fei-Lung Lai, Chun-Ren Cheng, Chun-Wen Cheng
  • Patent number: 11542151
    Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) apparatus. The MEMS apparatus includes a base substrate and a conductive routing layer disposed over the base substrate. A bump feature is disposed directly over the conductive routing layer. Opposing outermost sidewalls of the bump feature are laterally between outermost sidewalls of the conductive routing layer. A MEMS substrate is bonded to the base substrate and includes a MEMS device directly over the bump feature. An anti-stiction layer is arranged on one or more of the bump feature and the MEMS device.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Sung Chang, Fei-Lung Lai, Shang-Ying Tsai, Cheng Yu Hsieh
  • Publication number: 20220063994
    Abstract: In some embodiments, a sensor is provided. The sensor includes a microelectromechanical systems (MEMS) substrate disposed over an integrated chip (IC), where the IC defines a lower portion of a first cavity and a lower portion of a second cavity, and where the first cavity has a first operating pressure different than an operating pressure of the second cavity. A cap substrate is disposed over the MEMS substrate, where a first pair of sidewalls of the cap substrate partially define an upper portion of the first cavity, and a second pair of sidewalls of the cap substrate partially define an upper portion of the second cavity. A sensor area comprising a movable portion of the MEMS substrate and a dummy area comprising a fixed portion of the MEMS substrate are both disposed in the first cavity. A pressure enhancement structure is disposed in the dummy area.
    Type: Application
    Filed: November 11, 2021
    Publication date: March 3, 2022
    Inventors: Chun-Wen Cheng, Fei-Lung Lai, Kuei-Sung Chang, Shang-Ying Tsai
  • Patent number: 11254564
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of vias, a signal transmitting portion, a heater and a sensing material. The plurality of vias penetrates the substrate, wherein each of the plurality of vias includes a conductive or semiconductive portion surrounded by an oxide layer. The signal transmitting portion is disposed in the substrate, wherein adjacent vias of the plurality of vias surrounds the signal transmitting portion. The heater is electrically connected to the signal transmitting portion, and the sensing material is disposed over the heater and electrically connected to the substrate. A method of manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu, Fei-Lung Lai, Shiang-Chi Lin
  • Publication number: 20210354980
    Abstract: An integrated CMOS-MEMS device includes a first substrate having a CMOS device, a second substrate having a MEMS device, an insulator layer disposed between the first substrate and the second substrate, a dischargeable ground-contact, an electrical bypass structure, and a contrast stress layer. The first substrate includes a conductor that is conductively connecting to the CMOS devices. The electrical bypass structure has a conducting layer conductively connecting this conductor of the first substrate with the dischargeable ground-contact through a process-configurable electrical connection. The contrast stress layer is disposed between the insulator layer and the conducting layer of the electrical bypass structure.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 18, 2021
    Inventors: Eason Hsieh, Fei-Lung Lai, Kuei-Sung Chang
  • Patent number: 11174158
    Abstract: In some embodiments, a sensor is provided. The sensor includes a microelectromechanical systems (MEMS) substrate disposed over an integrated chip (IC), where the IC defines a lower portion of a first cavity and a lower portion of a second cavity, and where the first cavity has a first operating pressure different than an operating pressure of the second cavity. A cap substrate is disposed over the MEMS substrate, where a first pair of sidewalls of the cap substrate partially define an upper portion of the first cavity, and a second pair of sidewalls of the cap substrate partially define an upper portion of the second cavity. A sensor area comprising a movable portion of the MEMS substrate and a dummy area comprising a fixed portion of the MEMS substrate are both disposed in the first cavity. A pressure enhancement structure is disposed in the dummy area.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Fei-Lung Lai, Kuei-Sung Chang, Shang-Ying Tsai
  • Patent number: 11148936
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a metallization layer over the substrate, and a sensing structure over the metallization layer. The sensing structure includes an outgassing layer over the metallization layer, a patterned outgassing barrier in proximity to a top surface of the outgassing layer, the patterned outgassing barrier exposing a portion of the outgassing layer, and an electrode over the patterned outgassing barrier. The method for manufacturing the semiconductor device is also provided.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jung-Huei Peng, Chia-Hua Chu, Fei-Lung Lai, Shiang-Chi Lin
  • Publication number: 20210309508
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.
    Type: Application
    Filed: June 16, 2021
    Publication date: October 7, 2021
    Inventors: Kuei-Sung Chang, Chun-Wen Cheng, Fei-Lung Lai, Shing-Chyang Pan, Yuan-Chih Hsieh, Yi-Ren Wang
  • Patent number: 11099152
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: August 24, 2021
    Inventors: Yi-Shao Liu, Chun-Ren Cheng, Ching-Ray Chen, Yi-Hsien Chang, Fei-Lung Lai, Chun-Wen Cheng
  • Patent number: 11084713
    Abstract: An integrated CMOS-MEMS device includes a first substrate having a CMOS device, a second substrate having a MEMS device, an insulator layer disposed between the first substrate and the second substrate, a dischargeable ground-contact, an electrical bypass structure, and a contrast stress layer. The first substrate includes a conductor that is conductively connecting to the CMOS devices. The electrical bypass structure has a conducting layer conductively connecting this conductor of the first substrate with the dischargeable ground-contact through a process-configurable electrical connection. The contrast stress layer is disposed between the insulator layer and the conducting layer of the electrical bypass structure.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eason Hsieh, Fei-Lung Lai, Kuei-Sung Chang
  • Patent number: 11040870
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Sung Chang, Chun-Wen Cheng, Fei-Lung Lai, Shing-Chyang Pan, Yuan-Chih Hsieh, Yi-Ren Wang