Patents by Inventor Feipei Lai

Feipei Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7345909
    Abstract: An SRAM memory cell that has a relatively small power consumption when writing a write value of ‘0’ to the memory cell includes cross-coupled first and second inverters, at least one read access transistor for selectively coupling a respective read bit line to a common connection node of a respective one of the first and second inverters, a switching transistor for selectively coupling the second inverter to a ground terminal, and a write access transistor for selectively coupling the common connection node of the second inverter to a write bit line.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: March 18, 2008
    Inventors: Yen-Jen Chang, Feipei Lai, Chia-Lin Yang
  • Publication number: 20070297249
    Abstract: An SRAM memory cell that has a relatively small power consumption when writing a write value of ‘0’ to the memory cell includes cross-coupled first and second inverters, at least one read access transistor for selectively coupling a respective read bit line to a common connection node of a respective one of the first and second inverters, a switching transistor for selectively coupling the second inverter to a ground terminal, and a write access transistor for selectively coupling the common connection node of the second inverter to a write bit line.
    Type: Application
    Filed: September 23, 2004
    Publication date: December 27, 2007
    Inventors: Yen-Jen Chang, Feipei Lai, Chia-Lin Yang
  • Patent number: 5504914
    Abstract: An instruction multi-level boosting method in a compiler has the step of providing a plurality of ordinary registers to act as the destination registers for access by the ordinary instructions. At least one instruction is boosted and speculatively executed. The boosting method also has the step of providing a plurality of special registers corresponding to the ordinary registers, and acting as the destination registers for access by the boosted and speculatively executed instruction. Then, at the original position of the boosted instruction, the address of at least one ordinary register used in the boosted instruction is translated into the address of at least one corresponding special register. In this way, the compiler efficiency can be incressed; the need of requiring additional registers is lowered; and the cost thereof is reduced down because no complicated duplicating circuit is needed.
    Type: Grant
    Filed: June 23, 1993
    Date of Patent: April 2, 1996
    Assignee: National Science Council
    Inventor: Feipei Lai