Abstract: A thread structure in accordance to one or more embodiments includes a thread extending helically along a portion of a bit body in spaced thread turns, the thread having a crest extending between a first flank and a second flank and a root extending between the thread turns, the root having a curvature defined by a portion of an ellipse tangentially adjoining the first and second flank at respective flank transition points, the ellipse having a major axis extending parallel to the axis and a minor axis extending perpendicular to the major axis and through a root bottom.

Abstract: A device includes a coil configured in a loop topology starting from a first end and extending to a second end, a pair of inward extension legs configured to extend from the first end and the second end toward an interior side of the coil to a third end and a fourth end, respectively, a pair of outward extension legs configured to extend from the first end and the second end toward an exterior side of the coil to a fifth end and a sixth end, respectively, a first capacitor configured to provide a capacitive coupling between the first end and the second end, a second capacitor configured to provide a capacitive coupling between the third end and the fourth end, and a third capacitor configured to provide a capacitive coupling between the fifth end and the sixth end.

Abstract: A device having a substrate, a dielectric slab attached upon the substrate, a coil including a plurality of metal segments laid out on a first metal layer secured by the dielectric slab, the coil being substantially laterally symmetrical with respect to a central line from a top view perspective, and a shield laid out on a second metal layer secured by the dielectric slab and configured in a tree topology. The shield is substantially laterally symmetrical with respect to the central line from the top view perspective, the tree topology including a plurality of clusters of branches, wherein each of said plurality of clusters of branches is associated with a respective metal segment of the coil and includes a primary branch and at least one set of secondary branches that are branched from the primary branch, parallel to one another, and oriented at a substantially forty-five-degree angle with respect to the respective metal segment from the top view perspective.

Abstract: A method includes generating a reference clock using a crystal oscillator; generating a first clock based on the reference clock using a clock multiplier unit, in which a frequency of the first clock is higher than a frequency of the reference clock by a clock multiplier factor; generating a second lock based on the first clock using a frequency multiplying circuit in accordance with a frequency multiplying signal, in which a frequency of the second clock is higher than the frequency of the first clock by a factor that is equal to either five fourths or three halves, depending on whether the frequency multiplying signal is in a first state or in a second state; dividing down the second clock by a factor of two to generate a first LO (local oscillator) signal; dividing down the first LO signal by a factor of two to generate a second LO signal.

Abstract: An apparatus includes a phase interpolator configured to receive a four-phase signal and output a six-phase signal, and a summing network configured to receive the six-phase signal and output a two-phase signal, wherein: a first phase, a third phase, and a fifth phase of the six-phase signal are summed to generate a second phase of the two-phase signal, while a second phase, a fourth phase, and a sixth phase of the six-phase signal are summed to generate a first phase of the two-phase signal.

Abstract: Embodiments relate to a voltage oscillator (VCO) that uses a replica bias circuit to generate a cascode bias voltage. The VCO generate an output periodic signal having a frequency and phase that is less or not susceptible to voltage swings by using a bias voltage generated in a replica bias circuit that replicates a voltage-to-current converter in the VOC. The bias voltage is generated and regulated according to a power supply voltage that supplies power to the VCO to account for voltage variations in the power supply voltage.

Abstract: A thread structure in accordance to one or more embodiments includes a thread extending helically along a portion of a bit body in spaced thread turns, the thread having a crest extending between a first flank and a second flank and a root extending between the thread turns, the root having a curvature defined by a portion of an ellipse tangentially adjoining the first and second flank at respective flank transition points, the ellipse having a major axis extending parallel to the axis and a minor axis extending perpendicular to the major axis and through a root bottom.

Abstract: A method comprises: receiving a differential input signal; converting the differential input signal into a first transmitted current and a second transmitted current using a common-source differential pair biased by a bias current; launching the first transmitted current and the second transmitted current onto a first port of a differential transmission line; receiving a first received current and a second received current from a second port of the differential transmission line; buffering the first received current and the second received current into a first output current and a second output current, respectively, using a current buffer, wherein the current buffer comprises: a common-gate amplifier pair, a first cross-coupling network configured to provide a negative feedback on the input side of the current buffer to reduce an input impedance of the current buffer, and a second cross-coupling network configured to provide a positive feedback on the output side of the current buffer to boost an output impe

Abstract: A device for cold rolling a thread on a tubular support member of a rotary shouldered thread connection includes obtaining an original root depth of a thread root, cold rolling the thread until a minimum increased root depth tolerance is achieved.

Abstract: A method of cold rolling a thread on a tubular support member of a rotary shouldered thread connection includes obtaining an original root depth of a thread root, cold rolling the thread until a minimum increased root depth tolerance is achieved. The thread may be cold rolled with a wheel tip having an elliptical profile.

Abstract: A thread structure in accordance to one or more embodiments includes a thread extending helically along the cylindrical member in spaced thread turns, the thread having a crest extending between a first flank and a second flank and a root extending between the thread turns, the root having a curvature defined by a portion of an ellipse tangentially adjoining the first and second flank at respective flank transition points, the ellipse having a major axis extending parallel to the axis and a minor axis extending perpendicular to the major axis and through a root bottom.

Abstract: A manufacturing system that manufactures a downhole tool string, which includes a model that describes relationship between properties of the downhole tool string, properties of a borehole, properties of a formation, and properties of a mud cake formed on a surface of the borehole and a design device that iteratively determines contact parameters that describe one or more contact points expected between the downhole tool string and the mud cake based at least in part on the model, in which the contact parameters comprise contact force expected at each of the contact points, adjusts the properties of the downhole tool string to add a spacer at one of the contact points associated with highest contact force, and indicates location, type, or both of the spacer to enable the manufacturing system to attach the spacer to the downhole tool string before deployment of the downhole tool string in the borehole.

Abstract: Systems, devices and methods for analog echo cancellation for high speed full duplex data transmissions, which include a first set of differential nodes to receive reception data and transmission data, a second set of differential nodes to receive the transmission data, and a subtraction circuit to receive data from the first set of differential nodes and data from the second set of differential nodes. The subtraction circuit includes a plurality of capacitors to receive data from each of the first and second sets differential nodes, and a termination circuit for providing DC termination voltage to subtract the data of the second set of differential nodes from the data of the first set of differential nodes to eliminate echo from the reception data received at the first set differential nodes.

Abstract: Examples of front-end modules, apparatuses and methods for coupling compensation in a closed-loop digital pre-distortion (DPD) system are described. The closed-loop DPD circuit may include a PA and a loopback path. The PA may receive a PA input signal and amplify the PA input signal to provide a PA output signal proportional to a product of the PA input signal and a gain of the PA. The loopback path may receive the PA output signal to output a loopback signal. A forward coupling and a backward coupling may exist between the PA input signal and an output of the loopback path. The output of the loopback path may be proportional to a product of the PA output signal and a gain of the loopback path. The loopback path may include a coupling cancellation mechanism configured to cancel couplings between the PA input signal and the loopback signal.

Abstract: Methods and apparatus for providing adaptive biasing to power amplifiers. Adaptive bias circuits are configured to provide sharp turn on and/or current clamping to improve the efficiency of a power amplifier over a wide input signal bandwidth. Sharp turn on may be achieved using a subtraction technique to subtract outputs from multiple detectors. Clamping may be achieved using MOSFET device characteristics to pull the device from the triode region into the saturation, subtraction techniques to subtract the outputs from multiple detectors, and/or by using circuit devices, such as diodes.

Abstract: Embodiments of the present disclosure relate to methods and device for receiving PAM data stream. In an embodiment, a method comprises receiving a signal stream modulated with pulse amplitude modulation (PAM) associated with a plurality of bit patterns; determining boundary voltages for the plurality of bit patterns; and calibrating, based on the boundary voltages, a threshold voltage for use in recognition of the plurality of bit patterns. In this way, bit patterns may be accurately recognized based on the calibrated threshold voltage.

Abstract: A pump rod can include a body that includes a longitudinal axis; and a pin at an end of the body where the pin includes threads where the threads include tangential elliptical roots.

Abstract: Compositions and methods for identifying agents which 1) mimic salicyclic acid binding to human, animal and plant high mobility group box proteins or 2) alter activities of these HMGBs by binding in or around their salicyclic acid-binding sites and agents so identified are disclosed.

Abstract: A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.

Abstract: A method that calibrates a device for echo cancellation and a device with calibration for echo cancellation are provided. Devices may be calibrated such that the echo residual error is less than a threshold determined by the calibration accuracy. Non-ideal factors such as mismatch may be eliminated during calibration.