Abstract: A network packet processing device includes a parallel processing circuit, a packet dispatch circuit and a packet order-preserving processing circuit. The parallel processing circuit includes a plurality of packet processing circuits for processing different packets in parallel. Each packet processing circuit includes a network processing unit (NPU) core. The packet dispatch circuit distributes the packets to the packet processing circuits, respectively. The packet order-preserving processing circuit performs an order-preserved sending operation upon a plurality of processed packets generated by the parallel processing circuit, wherein the processed packets include first and second processed packets corresponding to first and second packets in the packets, respectively, and an order of the first and second processed packets in an output flow sent from the packet order-preserving processing circuit is the same as an order of the first and second packets in an input flow received by the packet dispatch circuit.

Abstract: A method for determining a process window of a patterning process based on a failure rate. The method includes obtaining a plurality of features printed on a substrate, grouping, based on a metric, the features into a plurality of groups, and generating, based on measurement data associated with a group of features, a base failure rate model for the group of features, wherein the base failure rate model identifies the process window related to the failure rate of the group of features. The method can further include generating, using the base failure rate model, a feature-specific failure rate model for a specific feature, wherein the feature-specific failure rate model identifies a feature-specific process window such that an estimated failure rate of the specific feature is below a specified threshold.

Abstract: A network packet processing device includes a hardware-accelerated forwarding circuit and a network processing unit (NPU). The hardware-accelerated forwarding circuit is used to receive a plurality of L4S packets from a network port and send the plurality of L4S packets to another network port through hardware-accelerated forwarding without intervention of a central processing unit (CPU). The NPU is used to perform ECN marking on at least a portion of the plurality of L4S packets.

Abstract: An imaging luminance, chromaticity, and viewing angle analyzer is provided, belonging to the technical field of optical instrument manufacturing, and including a housing. A turntable is disposed on an upper surface of the housing, a CCD electronic lens and a conical lens are disposed throughout an off-center point of the turntable, a rangefinder is disposed at the center of the turntable, a spectrometer and an RGB camera are disposed inside the housing, a through hole cooperating with the RGB camera and the spectrometer is provided in the upper surface of the housing, a filter switching apparatus cooperating with the through hole is disposed inside the housing between the through hole and the RGB camera, and a turntable drive apparatus for driving the turntable is also disposed inside the housing.

Abstract: An upload speed test method includes: during an upload speed test process, repeatedly checking whether at least one sending rate adjustment condition is met; and whenever it is determined that the at least one sending rate adjustment condition is met, adjusting a current sending rate to set an adjusted sending rate, and using the adjusted sending rate to transmit packets to a server.

Abstract: The present invention discloses an anti-full-throat diving device, an underwater communication device, a manufacturing method and a communication method therefor. The underwater communication device comprises a holding unit, a microphone unit and a housing. Among them, the housing has a chamber, a passage opening, an aperture, a front-facing side, and a noise reduction part. The passage opening and the aperture are respectively connected to the chamber. The aperture defines the front-facing side, and the noise reduction part is set on the inner wall of the housing for defining the chamber. The microphone unit is set in the chamber of the housing, and the holding unit is set in the housing.

Abstract: A network device includes a storage device, a hardware-accelerated forwarding circuit, and a network processing unit (NPU). The storage device stores a software flow table, where the software flow table includes a plurality of table entries. The hardware-accelerated forwarding circuit receives a first packet from a network, obtains a first hash value of the first packet, and determines that the first hash value encounters a hash collision in a hardware flow table. The NPU receives the first packet from the hardware-accelerated forwarding circuit, and deals with forwarding of the first packet according to forwarding information recorded in a table entry when the first packet hits the table entry of the software flow table.

Abstract: A method for forwarding a vector packet processing (VPP) is applicable to a forwarding path. The forwarding path includes an interface entrance, a data plane development kit (DPDK) input end, an entrance labeling-and-categorizing plug-in unit, one or more intermediate nodes, a Tx output end, an exit labeling-and-categorizing plug-in unit, and an interface exit. The vector packet processing forwarding method includes: executing a learning-and-recording mode for a preceding packet to obtain a learning result, and in the learning-and-recording mode, having the preceding packet entirely pass through the forwarding path; and executing an optimized acceleration mode for a subsequent packet, and in the optimized acceleration mode, based on the learning result, having the subsequent packet detour at least one intermediate node of the one or more intermediate nodes in the forwarding path.

Abstract: The present invention provides a loop detection method applicable to a mesh network including a plurality of links among a plurality of devices, including: creating a neighbor graph based on a topology maintenance message, wherein the neighbor graph represents a network structure of the mesh network; traversing the neighbor graph; and detecting whether there is a loop existing in the mesh network according to a result from traversing the neighbor graph.

Abstract: A preparation method of liquid crystal synergistic high-conductivity silicone rubber composite is provided, including following steps: firstly, synthesizing BP6; then synthesizing FLCPU; finally, mixing VMQ and FLCPU by mechanical blending, then adding conductive carbon black and 2,5-Dimethyl-2,5-bis(hexyl) vulcanizing agent in sequence, then obtaining FLCPU modified VMQ/CCB rubber compound; and hot-pressing the rubber compound on a flat vulcanizer to obtain a finished product, and detecting the material of the finished product before and after modification to extract data.

Abstract: A network device includes a storage device, a central processing unit (CPU), a hardware acceleration circuit, and a network processing unit (NPU). The storage device stores program codes. The CPU loads and executes the program codes to deal with a control function of a network speed test. The hardware acceleration circuit provides hardware-accelerated packet forwarding. The NPU interacts with the control function performed by the CPU, and deals with processing of data packets used for the network speed test. Transmission of the data packets between the network device and another network device is performed through the NPU and the hardware acceleration circuit, without intervention of the CPU.

Abstract: A buffer management apparatus includes a plurality of registers and a buffer block management circuit. The buffer block management circuit is used to communicate with software through the plurality of registers, and utilize pure hardware to manage a plurality of buffer blocks configured in a storage medium, for allowing the software to perform data access upon the plurality of buffer blocks.

Abstract: An embedded gateway system includes a processor, a first memory, a second memory, and a data prefetch circuit. The processor is used to execute a first program. The first memory is used to store a first data. The first memory and the second memory are external memories of the processor, and access latency of the second memory is lower that access latency of the first memory. The data prefetch circuit is used to perform a first data prefetch operation upon the first memory for reading a first prefetched data from the first memory and writing the first prefetched data into the second memory. Before a time point at which the processor executes a data access code segment of the first program to access the first data, the first data prefetch operation reads the first data from the first memory as the first prefetched data.

Abstract: A network packet processing apparatus includes a packet buffer, a ring buffer and a network processing unit (NPU). The packet buffer is used for storing a network packet. The ring buffer is used for storing a packet descriptor of the network buffer, where the packet descriptor includes a first field, and the first field is used for indirectly indicating a buffer address in the packet buffer at which the network packet is stored. The NPU is used for reading the packet descriptor from the ring buffer, and performing predetermined packet processing of the network packet according to the packet descriptor.

Abstract: A multi-core processor includes a plurality of processor cores and a data transfer circuit. The processor cores include a first processor core and a second processor core. The first processor core has a first buffer, and writes a first data into the first buffer. The second processor core has a second buffer. The data transfer circuit performs a polling operation upon the first buffer to check if the first buffer has data waiting to be transferred, and transfers the first data from the first buffer to the second buffer, wherein the first data is transferred inside the multi-core processor only.

Abstract: A network packet processing apparatus includes a first memory, a second memory, a direct memory access (DMA) controller, and a network processing unit (NPU). Access latency of the second memory is lower than access latency of the first memory. The DMA controller is used to write a network packet into the first memory, and write a partial packet content of the network packet into the second memory. The NPU reads the partial packet content from the second memory, and performs packet pre-processing of the network packet according to the partial packet content.

Abstract: A network processor includes a processor. The processor includes at least one processor core and a cache. The at least one processor core loads and executes program codes to deal with packet processing. The program codes include a network driver, a network stack of an operating system (OS) kernel, and a packet pre-learning module. The packet pre-learning module generates a fake packet, and sends the fake packet to the network stack of the OS kernel through the network driver. The cache caches at least a portion of instructions and data associated with processing of the fake packet that is performed by the network stack of the OS kernel.

Abstract: Selecting one or more lists of fields of view of a pattern layout for scanning electron microscope measurement and/or other inspection. A set of candidate fields of view is determined based on pattern groups of a pattern layout and a constraint on a characteristic of a given field of view. The characteristic of a given field of view includes a distance from the given field of view to another field of view and/or a size of the given field of view. The one or more lists are selected from the set of candidate fields of view according to prescribed criteria for combinations of fields of view included in the one or more lists. The prescribed criteria causes inclusion of an optimally diverse group of patterns in a predetermined number of lists of fields of view.

Abstract: A system and a method for performing field programmable gate array (FPGA) prototype verification on a tested circuit are provided. The system includes a packet generator, a scrambling circuit, the tested circuit and a checking circuit, wherein the scrambling circuit, the tested circuit and the checking circuit are implemented on an FPGA. The packet generator outputs multiple standard packets, wherein a length of each standard packet falls within a standard range. The scrambling circuit generates multiple scrambled packets according to the multiple standard packets to the tested circuit, to make the tested circuit generate multiple output packets according to the multiple scrambled packets, wherein a length of any scrambled packet falls outside the standard range. The checking circuit verifies operations of the tested circuit according to the multiple scrambled packets and the output packets.

Abstract: A method of hot spot ranking for a patterning process. The method includes obtaining (i) a set of hot spots of a patterning process, (ii) measured values of one or more parameters of the patterning process corresponding to the set of hot spots, and (ii) simulated values of the one or more parameters of the patterning process corresponding to the set of hot spots; determining a measurement feedback based on the measured values and the simulated values of the one or more parameters of the patterning process; and determining, via simulation of a process model of the patterning process, a ranking of a hot spot within the set of hot spots based on the measurement feedback.