Abstract: A network processor includes a processor. The processor includes at least one processor core and a cache. The at least one processor core loads and executes program codes to deal with packet processing. The program codes include a network driver, a network stack of an operating system (OS) kernel, and a packet pre-learning module. The packet pre-learning module generates a fake packet, and sends the fake packet to the network stack of the OS kernel through the network driver. The cache caches at least a portion of instructions and data associated with processing of the fake packet that is performed by the network stack of the OS kernel.

Abstract: Selecting one or more lists of fields of view of a pattern layout for scanning electron microscope measurement and/or other inspection. A set of candidate fields of view is determined based on pattern groups of a pattern layout and a constraint on a characteristic of a given field of view. The characteristic of a given field of view includes a distance from the given field of view to another field of view and/or a size of the given field of view. The one or more lists are selected from the set of candidate fields of view according to prescribed criteria for combinations of fields of view included in the one or more lists. The prescribed criteria causes inclusion of an optimally diverse group of patterns in a predetermined number of lists of fields of view.

Abstract: A system and a method for performing field programmable gate array (FPGA) prototype verification on a tested circuit are provided. The system includes a packet generator, a scrambling circuit, the tested circuit and a checking circuit, wherein the scrambling circuit, the tested circuit and the checking circuit are implemented on an FPGA. The packet generator outputs multiple standard packets, wherein a length of each standard packet falls within a standard range. The scrambling circuit generates multiple scrambled packets according to the multiple standard packets to the tested circuit, to make the tested circuit generate multiple output packets according to the multiple scrambled packets, wherein a length of any scrambled packet falls outside the standard range. The checking circuit verifies operations of the tested circuit according to the multiple scrambled packets and the output packets.

Abstract: A method of hot spot ranking for a patterning process. The method includes obtaining (i) a set of hot spots of a patterning process, (ii) measured values of one or more parameters of the patterning process corresponding to the set of hot spots, and (ii) simulated values of the one or more parameters of the patterning process corresponding to the set of hot spots; determining a measurement feedback based on the measured values and the simulated values of the one or more parameters of the patterning process; and determining, via simulation of a process model of the patterning process, a ranking of a hot spot within the set of hot spots based on the measurement feedback.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for load balancing of a network processing unit (NPU). A central processing unit (CPU) is coupled to the NPU and the NPU has multiple cores. The method, which is performed by the CPU, includes: reassigning a data stream processed by a first core in the NPU, which is under a high load, to a second core in the NPU, which is under a low load, where the low load is lower than the high load. The data stream is distinguished from other data streams by at least its quintuple, and the quintuple is composed of a source Internet Protocol (IP) address, a source port, a destination IP address, a destination port and a protocol type.

Abstract: A link aggregation load balancing apparatus includes a flow monitoring circuit and an initial allocation circuit. The flow monitoring circuit is arranged to monitor flows of a plurality of member ports belonging to a link aggregation group, for performing classification upon the plurality of member ports to generate a member port classification result. The initial allocation circuit is arranged to refer to the member port classification result for selecting a target member port from the plurality of member ports to act as a forward port of a data flow.

Abstract: A method for forwarding a vector packet processing (VPP) is applicable to a forwarding path. The forwarding path includes an interface entrance, a data plane development kit (DPDK) input end, an entrance labeling-and-categorizing plug-in unit, one or more intermediate nodes, a Tx output end, an exit labeling-and-categorizing plug-in unit, and an interface exit. The vector packet processing forwarding method includes: executing a learning-and-recording mode for a preceding packet to obtain a learning result, and in the learning-and-recording mode, having the preceding packet entirely pass through the forwarding path; and executing an optimized acceleration mode for a subsequent packet, and in the optimized acceleration mode, based on the learning result, having the subsequent packet detour at least one intermediate node of the one or more intermediate nodes in the forwarding path.

Abstract: A microfluidic system, including: a container, an ultrasound transmitter assembly, and a phononic crystal plate. The container is configured to accommodate a solution containing microparticles. The ultrasound transmitter assembly is configured to transmit ultrasonic waves to the phononic crystal plate, where the ultrasonic waves have a frequency which is the same as a resonance frequency of the phononic crystal plate. The phononic crystal plate is placed in the solution, and configured to generate a local acoustic field on a surface of the phononic crystal plate under excitation of the ultrasonic waves, and induce an acoustic microstreaming vortex to generate an acoustic streaming shear stress on the microparticles. The phononic crystal plate defines therein cavities, the respective cavities are arranged periodically in the phononic crystal plate, and all the respective cavities are filled with gas.

Abstract: Systems and methods for evaluating selected set of patterns of a design layout. A method herein includes obtaining (i) a first pattern set resulting from a pattern selection process, (ii) first pattern data associated with the first pattern set, (iii) characteristic data associated with the first pattern data, and (iv) second pattern data associated with a second pattern set. A machine learning model is trained based on the characteristic data, where the machine learning model being configured to predict pattern data for an input pattern. The second pattern set is input to the trained machine learning model to predict second pattern data of the second pattern set. The first pattern set is evaluated by comparing the second pattern data and the predicted second pattern data. If the evaluation indicates insufficient pattern coverage, additional patterns can be included to improve the pattern coverage.

Abstract: The application relates to an air conditioner/heat pump expansion function box and an air conditioner/heat pump heat storage refrigeration system, and belongs to the technical field of air conditioner/heat pump systems. Two distribution pipelines are arranged in the air conditioner/heat pump expansion function box body; each distribution pipeline comprises a main pipeline and at least one branch pipeline; the two ends of each main path are provided with an outdoor unit nut head and an indoor unit nut head respectively. The end portion, far away from the main path, of each branch path is provided with a radiation assembly nut head; an outdoor unit nut head is connected with an outdoor unit, an indoor unit nut head is connected with an indoor unit, and a radiation assembly nut head is connected with a radiation assembly.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an optical network unit (ONU) router for memory access control. The method, which is performed by a central processing unit (CPU), includes: obtaining an identification of a core; determining one from multiple allocated queues according to the identification of the core; and dequeuing one or more items in a shared resource pool starting from a slot that is pointed to by a take index, and enqueuing the one or more items into the determined allocated queue starting from an empty slot that is pointed to by a write index. Each item stored in the determined allocated queue includes a memory address range of a random access memory (RAM), so that the memory address range of the RAM has been reserved for the first core.

Abstract: A method for forwarding a vector packet processing (VPP) is applicable to a forwarding path. The forwarding path includes an Ethernet entrance, a data plane development kit (DPDK) input end, an entrance labeling-and-categorizing plug-in unit, one or more intermediate nodes, a Tx output end, an exit labeling-and-categorizing plug-in unit, and an Ethernet exit. The vector packet processing forwarding method includes: executing a learning-and-recording mode for a preceding packet to obtain a learning result, and in the learning-and-recording mode, having the preceding packet entirely pass through the forwarding path; and executing an optimized acceleration mode for a subsequent packet, and in the optimized acceleration mode, based on the learning result, having the subsequent packet detour some intermediate nodes of the one or more intermediate nodes in the forwarding path.

Abstract: This application discloses a path determining method and apparatus. The method includes: receiving a packet; and selecting a target path from a plurality of equal-cost paths in a first group of equal-cost multi-path (ECMP) entries in a forwarding table based on a first equal-cost multi-path ECMP identifier, and forwarding the packet based on the target path, where the first ECMP identifier indicates that at least one valid equal-cost path exists in the plurality of equal-cost paths in the first group of ECMP entries; and the first group of ECMP entries is a last-level ECMP entry in a plurality of levels of ECMP entries in the forwarding table. An ECMP identifier of each group of ECMP entries in each level of ECMP entries in the forwarding table may be used to determine whether a valid equal-cost path exists in the group of ECMP entries.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for load balancing of a network processing unit (NPU). A central processing unit (CPU) is coupled to the NPU and the NPU has multiple cores. The method, which is performed by the CPU, includes: reassigning a data stream processed by a first core in the NPU, which is under a high load, to a second core in the NPU, which is under a low load, where the low load is lower than the high load. The data stream is distinguished from other data streams by at least its quintuple, and the quintuple is composed of a source Internet Protocol (IP) address, a source port, a destination IP address, a destination port and a protocol type.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for analyzing an algorithm designed for running on a network processing unit (NPU). The method, which is performed by a processing unit, includes: loading and executing an executable program file on a virtual machine, which includes the algorithm that can be executed by the NPU; generating an instruction classification table during an execution of the executable program file, where the instruction classification table stores information about instructions that have been executed on the virtual machine, and which instruction category each instruction is related to; and generating an execution-cost statistics table according to the instruction classification table and an instruction cost table, thereby enabling the algorithm to be optimized according to content of the execution-cost statistics table.

Abstract: A buffer management apparatus includes a plurality of registers and a buffer block management circuit. The buffer block management circuit is used to communicate with software through the plurality of registers, and utilize pure hardware to manage a plurality of buffer blocks configured in a storage medium, for allowing the software to perform data access upon the plurality of buffer blocks.

Abstract: A link aggregation load balancing apparatus includes a flow monitoring circuit and an initial allocation circuit. The flow monitoring circuit is arranged to monitor flows of a plurality of member ports belonging to a link aggregation group, for performing classification upon the plurality of member ports to generate a member port classification result. The initial allocation circuit is arranged to refer to the member port classification result for selecting a target member port from the plurality of member ports to act as a forward port of a data flow.

Abstract: The present invention provides a method of implementing an ARM64-bit floating point emulator on a Linux system, which includes: running an ARM64-bit instruction on the Linux system; applying an instruction classifier to a first feature code of a machine code indicated by the ARM64-bit instruction to determine whether the ARM64-bit instruction is an ARM64-bit floating point instruction; and, if the ARM64-bit instruction is an ARM64-bit floating point instruction, applying the instruction classifier to a second feature code of the machine code indicated by the ARM64-bit instruction to determine the ARM64-bit floating point instruction to be a specific ARM64-bit floating point instruction.

Abstract: A method for determining a process window of a patterning process based on a failure rate. The method includes obtaining a plurality of features printed on a substrate, grouping, based on a metric, the features into a plurality of groups, and generating, based on measurement data associated with a group of features, a base failure rate model for the group of features, wherein the base failure rate model identifies the process window related to the failure rate of the group of features. The method can further include generating, using the base failure rate model, a feature-specific failure rate model for a specific feature, wherein the feature-specific failure rate model identifies a feature-specific process window such that an estimated failure rate of the specific feature is below a specified threshold.

Abstract: A method for forwarding a vector packet processing (VPP) is applicable to a forwarding path. The forwarding path includes an Ethernet entrance, a data plane development kit (DPDK) input end, an entrance labeling-and-categorizing plug-in unit, one or more intermediate nodes, a Tx output end, an exit labeling-and-categorizing plug-in unit, and an Ethernet exit. The vector packet processing forwarding method includes: executing a learning-and-recording mode for a preceding packet to obtain a learning result, and in the learning-and-recording mode, having the preceding packet entirely pass through the forwarding path; and executing an optimized acceleration mode for a subsequent packet, and in the optimized acceleration mode, based on the learning result, having the subsequent packet detour some intermediate nodes of the one or more intermediate nodes in the forwarding path.