Patents by Inventor Fei Ying Wong
Fei Ying Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230211975Abstract: The disclosure relates to an electronic component packing reel for a tape and reel packaging system and the electronic components are supported in pockets of a carrier tape wound around the reel, the packing reel includes: a central hub; two wall elements attached on both sides of the centrale hub defining a retaining space for retaining the carrier tape wound around the central hub; a hub insert arranged for placement of the hub insert over the central hub, the hub insert having an outer rim diameter for increasing a diameter of the central hub, and the hub insert includes at least two sections having mating locking means for interlocking the sections upon placement of the hub insert over the central hub.Type: ApplicationFiled: December 28, 2022Publication date: July 6, 2023Applicant: NEXPERIA B.V.Inventors: King Fai Poon, Tin Ho Wong, Fei Ying Wong
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Patent number: 10056343Abstract: Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure.Type: GrantFiled: January 7, 2016Date of Patent: August 21, 2018Assignee: Nexperia B.V.Inventors: Roelf A. J. Groenhuis, Kan Wae Lam, Clifford J. Lloyd, Chi Hoo Wan, Fei Ying Wong
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Patent number: 9418919Abstract: Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A second contact is relative to the first contact; the second contact has a split therein to provide first and second portions of the second contact arranged relative to one another to lessen tilting of a soldering condition involving attachment of the chip carrier to a printed circuit board.Type: GrantFiled: January 14, 2011Date of Patent: August 16, 2016Assignee: NXP B.V.Inventors: Roelf Anco Jacob Groenhuis, Markus Björn Erik Noren, Fei-ying Wong, Hei-ming Shiu
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Publication number: 20160211197Abstract: Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A second contact is relative to the first contact; the second contact has a split therein to provide first and second portions of the second contact arranged relative to one another to lessen tilting of a soldering condition involving attachment of the chip carrier to a printed circuit board.Type: ApplicationFiled: January 14, 2011Publication date: July 21, 2016Applicant: NXP B.V.Inventors: Roelf Anco Jacob GROENHUIS, Markus Björn Erik NOREN, Fei-ying WONG, Hei-ming SHIU
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Publication number: 20160118357Abstract: Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure.Type: ApplicationFiled: January 7, 2016Publication date: April 28, 2016Applicant: NXP B.V.Inventors: Roelf A.J. Groenhuis, Kan Wae Lam, Clifford J. Lloyd, Chi Hoo Wan, Fei Ying Wong
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Patent number: 9269690Abstract: Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure.Type: GrantFiled: December 6, 2013Date of Patent: February 23, 2016Assignee: NXP B.V.Inventors: Roelf A. J. Groenhuis, Kan Wae Lam, Clifford J. Lloyd, Chi Hoo Wan, Fei Ying Wong
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Publication number: 20150162298Abstract: Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure.Type: ApplicationFiled: December 6, 2013Publication date: June 11, 2015Applicant: NXP B.V.Inventors: Roelf A.J. Groenhuis, Kan Wae Lam, Clifford J. Lloyd, Chi Hoo Wan, Fei Ying Wong
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Publication number: 20120286399Abstract: In one embodiment, a method is provided for packaging a semiconductor die. A leadframe having a die-pad and one or more lead-pads is placed (502) on an assembly surface. The die-pad has a base portion (202) resting on the assembly surface, an upper portion (204) on the base portion extending laterally from the base portion, and a support arm (208) extending from and supporting the upper portion of die-pad. A semiconductor die (206) is wirebonded (504) to a top surface of the upper portion of the die-pad. The semiconductor die is wirebonded (506) to the one or more lead-pads (210). The semiconductor die and leadframe are encased (508) in a package material (802). The package material fills a space between the upper portion of the die-pad and the assembly surface. A portion of the support arm located in a cutting lane is removed (512).Type: ApplicationFiled: May 8, 2012Publication date: November 15, 2012Applicant: NXP B.V.Inventors: Tim BOETTCHER, Sven WALCZYK, Fei-Ying WONG, Pompeo UMALI, Roelf Anco Jacob GROENHUIS, Bernd ROHRMOSER, ChiFai LEE, Markus Bjoern Erik NOREN, PaulPangHing TSANG
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Publication number: 20120181678Abstract: Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A second contact is relative to the first contact; the second contact has a split therein to provide first and second portions of the second contact arranged relative to one another to lessen tilting of a soldering condition involving attachment of the chip carrier to a printed circuit board.Type: ApplicationFiled: January 14, 2011Publication date: July 19, 2012Applicant: NXP B.V.Inventors: Roelf Anco Jacob GROENHUIS, Markus Björn Erik NOREN, Fei-ying WONG, Hei-ming SHIU
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Patent number: 7301225Abstract: A lead frame (10) for a semiconductor device includes a first row of terminals (12) surrounding a die receiving area (14) and a second row of terminals (16) spaced from and surrounding the first row of terminals (12). The first and second rows of terminals (12, 16) have a first height (H1). The terminals (12) of the first row include a step (26) that has a greater height (H2). Bond wires (36) connecting die pads (34) to the first row terminals (12) extend over the second height H2 part of the terminal (12) and are attached to the first height H1 part of the terminal (12). The step (26) insures that the bond wires (36) attached to the stepped terminals (12) have a high wire kink profile so that they are less susceptible to damage in later process steps.Type: GrantFiled: February 28, 2006Date of Patent: November 27, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Fei Ying Wong, Wai Keung Ho, Ho Wang Wong
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Patent number: 7262494Abstract: An electronic device (60) including a first integrated circuit (IC) die (62) electrically connected to a first lead frame (64) and a second IC die (66) electrically connected to a second lead frame (68). The first lead frame (64) is electrically connected to the second lead frame (68) by at least one stud bump (72), which is selectively formed where an electrical connection between the first lead frame (64) and the second lead frame (68) is required. The first and second lead frames (64) and (68), the first and second IC dies (62) and (66), and the at least one stud bump (72) are encapsulated by a mold compound (74) to form a 3D package.Type: GrantFiled: March 16, 2005Date of Patent: August 28, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Hei Ming Shiu, On Lok Chau, Fei Ying Wong
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Patent number: 6838751Abstract: A leadframe (20) for a semiconductor device includes a paddle ring (22) having an inner perimeter (24), an outer perimeter (26), and a cavity (28) located within the inner perimeter (24) for receiving an integrated circuit die (30). A first row of terminals (32) surrounds the outer perimeter (26) and a second row of terminals (34) surrounds the first row of terminals (32). Each of the terminals of the first row of terminals (32) is individually connected to the paddle ring (22) and each of the terminals of the second row of terminals (34) is connected to one side of a connection bar (78, 79), which is connected to one of the terminals of the first row (32) or to the paddle ring (22).Type: GrantFiled: March 6, 2002Date of Patent: January 4, 2005Assignee: Freescale Semiconductor Inc.Inventors: Man Hon Cheng, Wai Wong Chow, Fei Ying Wong
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Publication number: 20030168719Abstract: A leadframe (20) for a semiconductor device includes a paddle ring (22) having an inner perimeter (24), an outer perimeter (26), and a cavity (28) located within the inner perimeter (24) for receiving an integrated circuit die (30). A first row of terminals (32) surrounds the outer perimeter (26) and a second row of terminals (34) surrounds the first row of terminals (32). Each of the terminals of the first row of terminals (32) is individually connected to the paddle ring (22) and each of the terminals of the second row of terminals (34) is connected to one side of a connection bar (78, 79), which is connected to one of the terminals of the first row (32) or to the paddle ring (22).Type: ApplicationFiled: March 6, 2002Publication date: September 11, 2003Inventors: Man Hon Cheng, Wai Wong Chow, Fei Ying Wong
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Publication number: 20020177254Abstract: A QFN semiconductor package (2) having a plurality of connection pads (4) and an embedded die (10) is disclosed. The connection pads (4) at least partially enclose a die receiving area (6). An insulator (8) is disposed in the die receiving area (6). The die (10) is attached to the insulator (8). The die (10) has a plurality of die bond pads. A plurality of connectors (12) connects the die bond pads to respective connection pads (4). An encapsulant (14) at least partially encapsulates the connection pads (4), insulator (8) and die (10). The connection pads (4) and insulator (8) have exposed surfaces on an outer surface of the encapsulant (14). The exposed surfaces are substantially co-planar with the outer surface of the encapsulant (14). A method of producing the semiconductor package (2) is also disclosed. Preferably, the insulator (8) includes a dispensed epoxy layer that is curable after the die is attached.Type: ApplicationFiled: April 9, 2002Publication date: November 28, 2002Inventors: Wai Wong Chow, Fei Ying Wong, Man Hon Cheng