Abstract: Examples described herein relate to an accelerator that includes an interface and circuitry coupled to the interface. In some examples, the circuitry is configured to access compressed data, decompress the compressed data, and output the decompressed data based on a call to an application programming interface (API). In some examples, based on a first call to the API having first values, the circuitry is to decompress at least a subset of the data and output at least one strict subset of the decompressed data. In some examples, based on a second call to the API having second values, the circuitry is to decompress an entirety of the data and output the decompressed data.

Abstract: A method is described. The method includes repeatedly reading accelerator telemetry data from register and/or memory space allocated for the keeping of the accelerator telemetry data and writing the accelerator telemetry data into a physical file structure within memory and/or mass storage. The method also includes repeatedly reading the accelerator telemetry data from the physical file structure and storing the accelerator telemetry data into virtual files that are visible to application software programs that invoke the accelerator. The accelerator telemetry data describes an input/output memory management unit’s performance regarding its translation of virtual addresses to physical addresses for the accelerator.

Abstract: An apparatus is described. The apparatus includes a memory management unit. The memory management unit is to receive a memory access request from an accelerator, wherein the memory access request includes a virtual address of a payload provided by an application that invokes the accelerator to perform a function on the payload, wherein. The memory access request also includes an identifier of the application's CPU process. The memory management unit is to translate the virtual address to a physical address to fetch the payload from a location allocated to the application within a memory.

Abstract: An apparatus is described. The apparatus includes a plurality of processing cores and at least one accelerator within a semiconductor chip package. The accelerator is to offload at least one task from the processing cores after boot-up of the processing cores and the accelerator. The accelerator is also to perform authentication of firmware during the boot-up. The firmware is to execute on one of the at least one accelerator.

Abstract: A machine-readable storage medium having program code that when processed by one or more processing cores causes a method to be performed. The method includes determining from program code that is scheduled for execution and/or is being scheduled for execution that an accelerator is expected to be invoked by the program code. The program code to implement one or more application software processes. The method also includes, in response to the determining, causing the accelerator to wake up from a sleep state before the accelerator is first invoked from the program code's execution.

Abstract: A hash calculation is performed using a portion or portions of a packet that is to be transmitted or is received. The calculated hash value can be used to select an entry that defines how the packet is to be handled. The performance of the lookup operation can be monitored and if the hash calculation is resulting in excessive collisions or extra processing steps are needed in connection with the lookup operation, then the inputs to the hash calculation can be modified to attempt to improve the performance of the lookup operation. For example, if performance of the lookup operation meets a threshold level to trigger a change in inputs, then different inputs can be selected and specified for use.