Abstract: A semiconductor package has a lead frame and a power die. The lead frame has a first die paddle with a cavity formed entirely therethrough. The power die, which has a lower surface, is mounted on the first die paddle such that a first portion of the lower surface is attached to the first die paddle using a solderless die-attach adhesive, and a second portion of the lower surface, is not attached to the first die paddle and abuts the cavity formed in the first die paddle such that the second portion is exposed.

Abstract: A packaged integrated circuit device includes a substrate module, leads, an IC die having first and second sets of die contact pads, and an encapsulant. The substrate module has upper and lower sets of conductive contacts on its upper and lower surfaces, respectively. The upper set of conductive contacts is electrically connected to the lower set of conductive contacts. The first set of die contact pads is electrically connected to the upper set of conductive contacts. The second set of die contact pads is electrically connected to the leads. Certain embodiments are a multi-form packaged device having both leads and conductive balls supporting different types of external connections, such as BGA and QFN.

Abstract: A grid array assembly is formed from an electrical insulating material with embedded solder deposits. A first portion of each of the solder deposits is exposed on a first surface of the insulating material and a second portion of each of the solder deposits is exposed on an opposite surface of the insulating material. A semiconductor die is mounted to the first surface of the insulating material and electrodes of the die are connected to the solder deposits with bond wires. The die, bond wires, and the first surface of the insulating material then are covered with a protective encapsulating material.

Abstract: A semiconductor die is packaged by providing a die assembly that includes a semiconductor die with an active surface and an opposite mounting surface with an attached thermally conductive substrate. The die assembly is mounted on a first surface of a lead frame die flag so that the thermally conductive substrate is sandwiched between the die flag and the semiconductor die. Bonding pads of the die are electrically connected with bond wires to lead frame lead fingers. A mold compound then encapsulates the semiconductor die, bond wires, and thermally conductive substrate. A second surface of the die flag is exposed through the mold compound.

Abstract: A semiconductor package has a lead frame and a power die. The lead frame has a first die paddle with a cavity formed entirely therethrough. The power die, which has a lower surface, is mounted on the first die paddle such that a first portion of the lower surface is attached to the first die paddle using a solderless die-attach adhesive, and a second portion of the lower surface, is not attached to the first die paddle and abuts the cavity formed in the first die paddle such that the second portion is exposed.

Abstract: A semiconductor die is packaged by providing a die assembly that includes a semiconductor die with an active surface and an opposite mounting surface with an attached thermally conductive substrate. The die assembly is mounted on a first surface of a lead frame die flag so that the thermally conductive substrate is sandwiched between the die flag and the semiconductor die. Bonding pads of the die are electrically connected with bond wires to lead frame lead fingers. A mold compound then encapsulates the semiconductor die, bond wires, and thermally conductive substrate. A second surface of the die flag is exposed through the mold compound.

Abstract: A grid array assembly is formed from an electrical insulating material with embedded solder deposits. A first portion of each of the solder deposits is exposed on a first surface of the insulating material and a second portion of each of the solder deposits is exposed on an opposite surface of the insulating material. A semiconductor die is mounted to the first surface of the insulating material and electrodes of the die are connected to the solder deposits with bond wires. The die, bond wires, and the first surface of the insulating material then are covered with a protective encapsulating material.

Abstract: A semiconductor wafer having multiple dies has a partially metallized backside. After wafer dicing, each of the multiple dies has, on its backside, a metallized area surrounded by a peripheral non-metallization ring. The non-metallization ring allows for easier optical inspection of the dies for determining the extent of any backside chipping caused by the wafer dicing. The peripheral non-metallization rings are generated by not metalizing the areas flanking the saw streets of the wafer.

Abstract: A wire bonding machine and a method for testing wire bond connection s using the wire bonding machine. The method includes providing a semiconductor assembly that has a semiconductor die mounted to a substrate, each of which has bonding pads. The method includes bonding a wire to one of the bonding pads to form a first wire bond. A shear force then is applied to the first wire bond. A fault signal is generated when a sensor detects the first wire bond moving during application of the shear force.

Abstract: A method for monitoring free air ball (FAB) formation during a wire bonding process includes attaching a dummy bond wire to an unused location on a first surface of a semiconductor chip carrier, extending the dummy bond wire a predetermined distance from the first surface such that a tip of the dummy bond wire is spaced from the first surface, and forming a dummy FAB at the tip of the bond wire. A profile of the dummy FAB is inspected with an imaging unit to identify any defects in the dummy FAB. An alarm is triggered and the wire bonding process is halted if the dummy FAB is defective so that bonding parameters may be adjusted. The wire bonding process is restarted after the bonding parameters have been adjusted.

Abstract: A method for monitoring free air ball (FAB) formation during a wire bonding process includes attaching a dummy bond wire to an unused location on a first surface of a semiconductor chip carrier, extending the dummy bond wire a predetermined distance from the first surface such that a tip of the dummy bond wire is spaced from the first surface, and forming a dummy FAB at the tip of the bond wire. A profile of the dummy FAB is inspected with an imaging unit to identify any defects in the dummy FAB. An alarm is triggered and the wire bonding process is halted if the dummy FAB is defective so that bonding parameters may be adjusted. The wire bonding process is restarted after the bonding parameters have been adjusted.