Abstract: The present disclosure relates to a terminal chip and a measurement method thereof. In an example, a terminal chip includes a computing subsystem and a security subsystem. The security subsystem is configured to measure the computing subsystem. A boot time of the security subsystem is earlier than a boot time of the computing subsystem. The security subsystem includes an integrity verification unit configured to perform integrity measurement on data in a boot process of the computing subsystem.

Abstract: The present invention provides a Streptococcus, which is a new species of the genus of Streptococcus, named as Streptococcus sp. 121, and is registered and deposited in GuangDong Microbial Culture Collection Center with the accession number of GDMCC No: 61195. After fermentation culture, the Streptococcus sp. 121 of the present invention can produce a stronger bacteriostatic active substance, which has relatively obvious antimicrobial effects on Klebsiella pneumoniae, Shigella dysenteriae, and the like, has a broad development space in prevention and treatment of diseases caused by Klebsiella pneumoniae and Shigella dysenteriae, and has a very good development and application prospect in antimicrobial drugs.

Abstract: The present application provides example terminal chips. One example terminal chip includes a security element, an application processor, and an interface module configured to transfer information between the application processor and the security element. The terminal chip includes a first power interface configured to receive power outside the terminal chip. A first power input port of the security element is connected to the first power interface, and at least one of the application processor or the interface module is connected to the first power interface. In the example terminal chip, a power supply port of the security element is connected to a power supply port of the application processor or the interface module of the terminal chip.

Abstract: A chip, including a selector, a one-time programmable (OTP) device, and a controller, where the controller is separately coupled to a selection end of the selector and the OTP device, and the controller is configured to detect a device value of the OTP device, and provide a first selection signal when the device value of the OTP device is within a first preset range. A first input end of the selector is configured to receive access data, a second input end of the selector is configured to receive a preset invalid value, and an output end of the selector is coupled to the OTP device. The selector is configured to control the data received by the second input end to be output from the output end of the selector when the first selection signal is input.

Abstract: A data processing method and apparatus relate to the field of communications technologies and applicable to data processing used to resolve a low security problem of data stored in a memory. A memory encryption/decryption (MED) apparatus receives a data write command, encrypts to-be-written data, scrambles an address to which data is to be written, and then saves a cyclic redundancy check (CRC) code of the to-be-written data and encrypted to-be-written data in a memory according to a scrambled address to which data is to be written. Solutions provided in the embodiments of the present disclosure are.

Abstract: The present application provides example terminal chips. One example terminal chip includes a security element, an application processor, and an interface module configured to transfer information between the application processor and the security element. The terminal chip includes a first power interface configured to receive power outside the terminal chip. A first power input port of the security element is connected to the first power interface, and at least one of the application processor or the interface module is connected to the first power interface. In the example terminal chip, a power supply port of the security element is connected to a power supply port of the application processor or the interface module of the terminal chip.

Abstract: A chip, including a selector, a one-time programmable (OTP) device, and a controller, where the controller is separately coupled to a selection end of the selector and the OTP device, and the controller is configured to detect a device value of the OTP device, and provide a first selection signal when the device value of the OTP device is within a first preset range. A first input end of the selector is configured to receive access data, a second input end of the selector is configured to receive a preset invalid value, and an output end of the selector is coupled to the OTP device. The selector is configured to control the data received by the second input end to be output from the output end of the selector when the first selection signal is input.

Abstract: The embodiments of the present invention disclose a bus security protection apparatus, including: a first check module, configured to check operation data, to generate a first check code; a first conversion module, configured to perform an exclusive-OR logical operation on the operation data and a polarity indication signal, to obtain polarity reversal data; a first encryption/decryption module, configured to perform an exclusive-OR logical operation on the polarity reversal data and preset scrambling data, to obtain encrypted data; a second encryption/decryption module, configured to perform an exclusive-OR logical operation on the encrypted data and the preset scrambling data, to obtain decrypted data; a second conversion module, configured to perform an exclusive-OR logical operation on the decrypted data and the polarity indication signal, to obtain decrypted conversion data; and a second check module, configured to: check the decrypted conversion data, to generate a second check code.

Abstract: A data processing method and apparatus relate to the field of communications technologies and applicable to data processing used to resolve a low security problem of data stored in a memory. A memory encryption/decryption (MED) apparatus receives a data write command, encrypts to-be-written data, scrambles an address to which data is to be written, and then saves a cyclic redundancy check (CRC) code of the to-be-written data and encrypted to-be-written data in a memory according to a scrambled address to which data is to be written. Solutions provided in the embodiments of the present disclosure are.