Abstract: A gate drive circuit and a display panel. The gate drive circuit includes one or more shift register groups. Each of the shift register groups includes N shift adjacent registers that output in sequence, with N being an integer greater than or equal to 3. Each of the shift registers includes a first output stage and a frequency division control module. The first output stage is configured to output a gate drive signal. The frequency division control module is configured to control outputting of the gate drive signal based on a refresh frequency. A control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.

Abstract: A display panel and a display device are provided, improving the stability of output signals from a gate driving circuit by connecting a first capacitor and a second capacitor to a second power line which is also connected to a second output transistor. This configuration increases the overall capacitance on the second power line, reduces the voltage drop across the second power line, and mitigates the issue of fluctuations in the high-level output of conventional GOA circuits affecting the stability of the output signals.

Abstract: A display including a pixel circuit is provided. The pixel circuit includes a driving transistor, a writing transistor connected in series between a data line and the second node or the third node, an initialization module, and a compensation transistor connected in series between the first node and the second node or the third node. In the driving transistor, a gate is connected to the first node, a first electrode is connected to the second node, and a second electrode is connected to the third node. A gate of the writing transistor is connected to a scanning signal. The initialization module is connected to the first, second, and/or third nodes to perform resetting. The compensation transistor remains a turned-on state in only one continuous time period in each frame, and the initialization module and the writing transistor turn on in a time-sharing manner in the continuous time period.

Abstract: A gate driving module and a display panel, including a plurality of cascaded gate driving circuits. each of the gate driving circuits includes a stage transmission unit, an output unit, a stage transmission frequency division control unit, and an output frequency division control unit. The stage transmission frequency division control unit controls a stage transmission output unit to output the current-stage stage transmission signal based on the signals from the third node and one of the first node and the second node. The output frequency division control unit controls the signal from the third node based on the frequency division control signal to control the output unit to output a current-stage gate control signal.

Abstract: A gate drive circuit and a display panel. The gate drive circuit includes one or more shift register groups. Each of the shift register groups includes N shift adjacent registers that output in sequence, with N being an integer greater than or equal to 3. Each of the shift registers includes a first output stage and a frequency division control module. The first output stage is configured to output a gate drive signal. The frequency division control module is configured to control outputting of the gate drive signal based on a refresh frequency. A control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.

Abstract: A display including a pixel circuit is provided. The pixel circuit includes a driving transistor, a writing transistor connected in series between a data line and the second node or the third node, an initialization module, and a compensation transistor connected in series between the first node and the second node or the third node. In the driving transistor, a gate is connected to the first node, a first electrode is connected to the second node, and a second electrode is connected to the third node. A gate of the writing transistor is connected to a scanning signal. The initialization module is connected to the first, second, and/or third nodes to perform resetting. The compensation transistor remains a turned-on state in only one continuous time period in each frame, and the initialization module and the writing transistor turn on in a time-sharing manner in the continuous time period.

Abstract: A gate driving unit and a display panel are provided by the present disclosure. In a writing frame of the display panel, a clock signal has a plurality of transitions between an active level state and an in active level state. In a plurality of holding frames of the display panel, the clock signal has a plurality of first periods holding the inactive level state, and the clock signal has a plurality of transitions between the active level state and the inactive level state in a second period between two adjacent first periods.

Abstract: The present application provides a gate driving unit and a display device, where the gate driving unit includes a plurality of gate driving circuits and a frequency division control line for transmitting a frequency division control signal to the plurality of gate driving circuits. Each of the gate driving circuits includes a frequency division control module, an output module and a frequency division control module, where the frequency division control module controls signal transmission between the output module and one of a first node and a second node according to a frequency division control signal and a signal from the first node or the second node of the frequency division control module.

Abstract: A gate driving unit and a display panel are provided by the present disclosure. In a writing frame of the display panel, a clock signal has a plurality of transitions between an active level state and an in active level state. In a plurality of holding frames of the display panel, the clock signal has a plurality of first periods holding the inactive level state, and the clock signal has a plurality of transitions between the active level state and the inactive level state in a second period between two adjacent first periods.

Abstract: The present application provides a gate driving module and a display panel. The gate driving module includes a plurality of cascaded gate driving circuits and a frequency division control line electrically connected thereto (for transmitting a frequency division control signal). Each of the gate driving circuits includes a gate control unit for receiving a gate control signal generated by an upper stage of gate driving circuit, an output unit electrically connected to the gate control unit via a first node and a second node (for outputting the gate signal and transmitting it to a lower stage of gate driving circuit), and a frequency division control unit electrically connected between the gate control unit and the output unit (for controlling a signal from one of the first node and the second node according to the frequency division control signal) to realize a frequency division function.

Abstract: A gate drive circuit and a display panel. The gate drive circuit includes one or more shift register groups. Each of the shift register groups includes N shift adjacent registers that output in sequence, with N being an integer greater than or equal to 3. Each of the shift registers includes a first output stage and a frequency division control module. The first output stage is configured to output a gate drive signal. The frequency division control module is configured to control outputting of the gate drive signal based on a refresh frequency. A control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.

Abstract: The present application provides an organic light emitting diode (OLED) display panel and an OLED device. The OLED display panel includes dummy traces disposed on a side of the anode adjacent to the signal traces. At least one of the fanout traces and at least one of the dummy traces are disposed corresponding to a position where the anode is disposed. Each of the fanout traces passing through each of the subpixels and each of the dummy traces passing through each of the subpixels are both symmetrical about a center of the anode of each of the subpixels, so as to improve uniformity of traces in the display area and improve flatness and symmetry of the anode, thereby improving display defect of the display panel.

Abstract: The present invention provides a display panel and an electronic apparatus, including a first display part and a second display part, a plurality of second gate driving units electrically connected to the second display part and arranged in cascade, a plurality of first gate driving units electrically connected to the first display part and arranged in cascade. A first gate driving unit including a first output unit for transmitting a first voltage to an output terminal in response to a voltage of a first node, a second output unit for transmitting a second voltage to the output terminal in response to a voltage of a second node, an output terminal electrically connected to a corresponding first sub-pixel, a constant voltage control unit electrically connected to a first node or a second node.

Abstract: A gate drive circuit and a display panel. The gate drive circuit includes one or more shift register groups. Each of the shift register groups includes N shift adjacent registers that output in sequence, with N being an integer greater than or equal to 3. Each of the shift registers includes a first output stage and a frequency division control module. The first output stage is configured to output a gate drive signal. The frequency division control module is configured to control outputting of the gate drive signal based on a refresh frequency. A control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.

Abstract: The present disclosure discloses a display panel in which a second data line in a display area is located between a first data line and a third data line, and a spacing between the first data line and the second data line is less than a spacing between the third data line and the second data line. A second pad is located between a first pad and a third pad in a direction perpendicular to the display area pointing to a binding area, the first pad is electrically connected to the first data line, the second pad is electrically connected to the third data line, and the third pad is electrically connected to the second data line.

Abstract: A display including a pixel circuit is provided. The pixel circuit includes a driving transistor, a writing transistor connected in series between a data line and the second node or the third node, an initialization module, and a compensation transistor connected in series between the first node and the second node or the third node. In the driving transistor, a gate is connected to the first node, a first electrode is connected to the second node, and a second electrode is connected to the third node. A gate of the writing transistor is connected to a scanning signal. The initialization module is connected to the first, second, and/or third nodes to perform resetting. The compensation transistor remains a turned-on state in only one continuous time period in each frame, and the initialization module and the writing transistor turn on in a time-sharing manner in the continuous time period.

Abstract: The present application provides a gate driving module and a display panel. The gate driving module includes a plurality of cascaded gate driving circuits and a frequency division control line electrically connected thereto (for transmitting a frequency division control signal). Each of the gate driving circuits includes a gate control unit for receiving a gate control signal generated by an upper stage of gate driving circuit, an output unit electrically connected to the gate control unit via a first node and a second node (for outputting the gate signal and transmitting it to a lower stage of gate driving circuit), and a frequency division control unit electrically connected between the gate control unit and the output unit (for controlling a signal from one of the first node and the second node according to the frequency division control signal) to realize a frequency division function.

Abstract: The present application provides a gate driving unit and a display device, where the gate driving unit includes a plurality of gate driving circuits and a frequency division control line for transmitting a frequency division control signal to the plurality of gate driving circuits. Each of the gate driving circuits includes a frequency division control module, an output module and a frequency division control module, where the frequency division control module controls signal transmission between the output module and one of a first node and a second node according to a frequency division control signal and a signal from the first node or the second node of the frequency division control module.

Abstract: A gate drive circuit and a display panel. The gate drive circuit includes one or more shift register groups. Each of the shift register groups includes N shift adjacent registers that output in sequence, with N being an integer greater than or equal to 3. Each of the shift registers includes a first output stage and a frequency division control module. The first output stage is configured to output a gate drive signal. The frequency division control module is configured to control outputting of the gate drive signal based on a refresh frequency. A control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.

Abstract: The present application discloses a display panel in which a second data line in a display area is located between a first data line and a third data line, and a spacing between the first data line and the second data line is less than a spacing between the third data line and the second data line. A second pad is located between a first pad and a third pad in a direction perpendicular to the display area pointing to a binding area, the first pad is electrically connected to the first data line, the second pad is electrically connected to the third data line, and the third pad is electrically connected to the second data line.