Patents by Inventor Feiyu JIANG

Feiyu JIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12086049
    Abstract: Techniques for capacity management in computing systems are disclosed herein. In one embodiment, a method includes analyzing data representing a number of enabled users or a number of provisioned users to determine whether the analyzed data represents an anomaly based on historical data. The method can also include upon determining that the data represents an anomaly, determining a conversion rate between a change in the number of enabled users or the number of provisioned users and a change in a number of active users of the computing service and deriving a future value of the number of active users of the computing service based on both the detected anomaly and the determined conversion rate. The method can further include allocating and provisioning an amount of the computing resource in the distributed computing system in accordance with the determined future value of the active users of the computing resource.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: September 10, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jieqiu Chen, Yow-Gwo Wang, Qizhi Xu, Feiyue Jiang, Harsh Mahendra Mehta, Boon Yeap, Dimple Kaul
  • Patent number: 11848062
    Abstract: A voltage control method and a voltage control circuit for an anti-fuse memory array, including: obtaining a storage data address, dividing the storage data address into multiple subdata addresses, decoding each subdata address to obtain a corresponding group of decoder output signals, converting the corresponding group of decoder output signals into a group of control signals by a corresponding group of high voltage converters; connecting multiple groups of data selectors in series, outputting selection voltages input to each group of data selectors to an anti-fuse unit under the control of the corresponding group of control signals; programming or reading an anti-fuse unit; the selection voltages include one of a programming selection voltage, a reading selection voltage, and a non-designated selection voltage. The present disclosure reduces the number of transistors and saves layout areas when the programming or reading operation is performed.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: December 19, 2023
    Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Yan Wang, Peijian Zhang, Mingyuan Xu, Xian Chen, Feiyu Jiang, Xiyi Liao, Sheng Qiu, Zhengyuan Zhang, Ruzhang Li, Hequan Jiang, Yonghong Dai
  • Publication number: 20230214308
    Abstract: Techniques for capacity management in computing systems are disclosed herein. In one embodiment, a method includes analyzing data representing a number of enabled users or a number of provisioned users to determine whether the analyzed data represents an anomaly based on historical data. The method can also include upon determining that the data represents an anomaly, determining a conversion rate between a change in the number of enabled users or the number of provisioned users and a change in a number of active users of the computing service and deriving a future value of the number of active users of the computing service based on both the detected anomaly and the determined conversion rate. The method can further include allocating and provisioning an amount of the computing resource in the distributed computing system in accordance with the determined future value of the active users of the computing resource.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Inventors: Jieqiu Chen, Yow-Gwo Wang, Qizhi Xu, Feiyue Jiang, Harsh Mahendra Mehta, Boon Yeap, Dimple Kaul
  • Publication number: 20230197178
    Abstract: A voltage control method and a voltage control circuit for an anti-fuse memory array, including: obtaining a storage data address, dividing the storage data address into multiple subdata addresses, decoding each subdata address to obtain a corresponding group of decoder output signals, converting the corresponding group of decoder output signals into a group of control signals by a corresponding group of high voltage converters; connecting multiple groups of data selectors in series, outputting selection voltages input to each group of data selectors to an anti-fuse unit under the control of the corresponding group of control signals; programming or reading an anti-fuse unit; the selection voltages include one of a programming selection voltage, a reading selection voltage, and a non-designated selection voltage. The present disclosure reduces the number of transistors and saves layout areas when the programming or reading operation is performed.
    Type: Application
    Filed: September 1, 2020
    Publication date: June 22, 2023
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Yan WANG, Peijian ZHANG, Mingyuan XU, Xian CHEN, Feiyu JIANG, Xiyi LIAO, Sheng QIU, Zhengyuan ZHANG, Ruzhang LI, Hequan JIANG, Yonghong DAI