Abstract: An integrated chip including a first source/drain region and a second source/drain region in a semiconductor substrate and laterally spaced apart along a top surface of the substrate. A gate dielectric layer is over the substrate and extends laterally between the first source/drain region and the second source/drain region. A thickness of the gate dielectric layer along a first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer. A trench isolation layer extends along gate dielectric layer. A first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer. A gate layer is directly over the gate dielectric layer and between the first source/drain region and the second source/drain region. A first sidewall of the gate layer is directly over the gate dielectric layer and laterally setback from the first sidewall of the gate dielectric layer.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are provided. The method includes: receiving a semiconductor substrate; forming a first well region and a second well region within the semiconductor substrate; forming a first dielectric layer on the semiconductor substrate between the first well region and the second well region; forming an interconnect structure comprising a second dielectric layer over the semiconductor substrate; and depositing a conductive layer in the interconnect structure over the second dielectric layer. The conductive layer serves as a first gate electrode of a first transistor in a first zone of the semiconductor substrate.

Abstract: A Schottky diode includes a substrate, a first drift region in the substrate, a second drift region in the substrate, a first dielectric layer disposed over the substrate, a first doped region in the first drift region, a second doped region in the second drift region, a third doped region in the first drift region, and a metal field plate disposed over the first dielectric layer. The first drift region and the first doped region include a first conductivity type. The second drift region, the second doped region and third doped region include a second conductivity type complementary to the first conductivity type. The first dielectric layer overlaps a portion of the first drift region and a portion of the second drift region. The second doped region is separated from the first doped region.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are provided. The method includes: receiving a semiconductor substrate; forming a first well region and a second well region within the semiconductor substrate; forming a gate dielectric layer in the semiconductor substrate between the first well region and the second well region; forming a first gate electrode over the semiconductor substrate and overlapping the gate dielectric layer; forming a conductive layer in an interconnect structure over the first gate electrode; and electrically connecting the conductive layer to the first gate electrode.

Abstract: An integrated chip including a first source/drain region and a second source/drain region along a semiconductor substrate. A channel region extends along the substrate from the first source/drain region to the second source/drain region. The gate electrode is between the first and second source/drain regions. The gate electrode has first and second outer sidewalls and a bottom surface extending from the first outer sidewall to the second outer sidewall. The gate dielectric layer is between the gate electrode and the channel region. A lateral portion of the gate dielectric layer extends laterally along the bottom surface of the gate electrode. First and second vertical portions of the gate dielectric layer extend upward from the lateral portion along the first and second outer sidewalls of the gate electrode.

Abstract: A semiconductor structure includes a gate structure, an isolation structure, a source region, a drain region, a source contact structure, and a drain contact structure. The gate structure is disposed over a substrate and extends in a first direction. The isolation structure is disposed between the gate structure and the substrate. The source region and the drain region are disposed at two sides of the isolation structure, and extend in the first direction. The source contact structure is coupled to the source region, and the drain contact structure is coupled to the drain region. Each of the source contact structure and the drain contact structure has a strip configuration and extends in the first direction.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.

Abstract: A semiconductor die in a semiconductor package includes a through-substrate capacitor structure that extends through the device layer of the semiconductor die. The through-substrate capacitor structure may be electrically connected to a first interconnect layer on a first side of the semiconductor die, and to a second interconnect layer on a second side of the semiconductor die opposing the first side. Forming the through-substrate capacitor structure through the device layer of the semiconductor die enables the through-substrate capacitor structure to be formed to have a high aspect ratio, which provides for greater surface area for a bottom electrode and a top electrode of the through-substrate capacitor structure. The greater surface area enables a higher capacitance to be achieved for the through-substrate capacitor structure.

Abstract: The gate dielectric layer of a transistor includes a central region and one or more edge regions. The thickness of the central region is less than the thickness of the plurality of edge regions. This increases the corner oxide thickness and reduces the double hump phenomenon, improving performance without needing an extra mask.

Abstract: One or more dielectric inserts are formed in a through-substrate interconnect structure to prevent, minimize, and/or otherwise reduce the amount of dishing that occurs in the top surface of the through-substrate interconnect structure during planarization of the through-substrate interconnect structure. The dielectric insert(s) are formed of a dielectric material having a hardness that is greater than the hardness of the metal material of the through-substrate interconnect structure. The greater hardness enables the dielectric insert(s) to resist material removal during planarization of the through-substrate interconnect structure, which enables a high uniformity in the material removal rates across the top surface of the through-substrate interconnect structure to be achieved.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a gate electrode, a first doped region, a second doped region, and a dummy gate electrode. The gate electrode is disposed on the substrate. The first doped region and the second doped region are disposed on two sides of the gate electrode. The dummy gate electrode is disposed on the substrate and between the gate electrode and the second doped region.

Abstract: The present disclosure relates to a semiconductor device with a hybrid fin-dielectric region. The semiconductor device includes a substrate, a source region and a drain region laterally separated by a hybrid fin-dielectric (HFD) region. A gate electrode is disposed above the HFD region and the HFD region includes a plurality of fins covered by a dielectric and separated from the source region and the drain region by the dielectric.

Abstract: A Schottky diode includes a substrate, a first drift region in the substrate, a second drift region in the substrate, a first dielectric layer disposed over the substrate, a first doped region in the first drift region, a second doped region in the second drift region, a third doped region in the first drift region, and a metal field plate disposed over the first dielectric layer. The first drift region and the first doped region include a first conductivity type. The second drift region, the second doped region and third doped region include a second conductivity type complementary to the first conductivity type. The first dielectric layer overlaps a portion of the first drift region and a portion of the second drift region. The second doped region is separated from the first doped region.

Abstract: A semiconductor 3D capacitor includes a semiconductor electrode disposed in a semiconductor substrate, a metal electrode over the semiconductor electrode, and an isolation structure between the semiconductor electrode and the metal electrode. The isolation structure includes a dielectric feature between the semiconductor electrode and the metal electrode, and a dielectric layer between the dielectric feature and the metal electrode. A bottom surface of the metal electrode is between a topmost surface of the dielectric feature and a bottom surface of the dielectric feature in a direction perpendicular to a surface of the semiconductor substrate.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a deep trench isolation (DTI), an interconnect structure, and a conductive pillar. The DTI is disposed in the substrate and the interconnect structure is disposed over the substrate. The conductive pillar extends from the interconnect structure toward the substrate and penetrates the DTI.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a deep trench isolation (DTI), an interconnect structure, and a conductive pillar. The DTI is disposed in the substrate and the interconnect structure is disposed over the substrate. The conductive pillar extends from the interconnect structure toward the substrate and penetrates the DTI. A method of manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor device and a method of fabricating the same are provided. The method includes steps of forming a source region and a drain region in a substrate; forming a gate structure on the substrate, wherein the source region and the drain region are disposed on opposite sides of the gate structure and separated from the gate structure by a distance; depositing an inter-layer dielectric (ILD) layer over the substrate and the gate structure; forming a first trench in the ILD layer, wherein the first trench exposes a first portion of the gate structure and overlies an area between the gate structure and one of the source and drain regions from a top-view perspective; and depositing a first conductive material in the first trench to form a conductive plate, wherein the conductive plate is electrically connected to the gate structure.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a transistor, and a capacitor structure. The transistor includes a gate electrode material. The capacitor structure includes a first electrode and a second electrode including the gate electrode material. The capacitor structure also includes a plurality of first conductive features disposed over the first electrode and a plurality of conductive vias disposed over a corresponding one of the plurality of first conductive features. The capacitor structure further includes a third electrode over the plurality of conductive vias and electrically connected to the first electrode through the plurality of first conductive features and the plurality of conductive vias.

Abstract: Transistors with strained source drain (SDD) structures are suitable for high voltage applications. A gate stack is present upon the substrate that includes a gate dielectric layer and a gate structure upon the gate dielectric layer. A gate spacer is present on the sidewalls of the gate stack. Two lightly doped drain (LDD) regions extend from below the gate stack towards opposite sides of the gate stack. A plurality of strained source and drain (SSD) structures are present within each LDD region. The SSD structures do not extend below the gate spacers. The transistor can be used in high voltage devices and still avoid junction breakdown.