Abstract: Techniques and apparatuses are described that implement smartphone-based power-efficient radar processing and memory provisioning for detecting gestures. The described techniques map different situations that occur with a user to different memory states. A radar processing system's memory management module allocates at least one memory pool according to an active memory state. As the radar system detects different situations that occur with the user, the memory management module reallocates the memory pool for the appropriate memory state, which can adjust a power mode of the radar system. In some cases, physically separate memories may be allocated for different memory states, which respectively include one or more sequences that are executed by different processors. The memory management module enables efficient use of available power and available memory for radar processing such that a total amount of power and a total size of memory used may be significantly reduced for detecting gestures.

Abstract: Techniques and apparatuses are described that implement smartphone-based power-efficient radar processing and memory provisioning for detecting gestures. The described techniques map different situations that occur with a user to different memory states. A radar processing system's memory management module allocates at least one memory pool according to an active memory state. As the radar system detects different situations that occur with the user, the memory management module reallocates the memory pool for the appropriate memory state, which can adjust a power mode of the radar system. In some cases, physically separate memories may be allocated for different memory states, which respectively include one or more sequences that are executed by different processors. The memory management module enables efficient use of available power and available memory for radar processing such that a total amount of power and a total size of memory used may be significantly reduced for detecting gestures.

Abstract: Various embodiments of techniques related to sample clock timing acquisition are provided. In one aspect, a method includes a first communication device receiving a wireless communication signal from a second communication device. The method also includes detecting a primary synchronization signal in the wireless communication signal. The method further includes estimating, based at least in part on the primary synchronization signal, a frequency offset between a sample clock timing frequency of the first communication device and a sample clock timing frequency of the second communication device.

Abstract: Various embodiments of primary synchronization signal detection are provided. In one aspect, a method receives one or more signals at one or more antennas of a receiver. The method processes the one or more received signals by decimation filtering the one or more received signals to provide one or more decimated signals, each of the one or more decimated signals having a predetermined symbol size, and enumerating correlation of the one or more decimated signals with a plurality of reference signals to provide correlation results. The method then detects a primary synchronization signal (PSS) based on the correlation results.

Abstract: Various embodiments of primary synchronization signal detection are provided. In one aspect, a method receives one or more signals at one or more antennas of a receiver. The method processes the one or more received signals by decimation filtering the one or more received signals to provide one or more decimated signals, each of the one or more decimated signals having a predetermined symbol size, and enumerating correlation of the one or more decimated signals with a plurality of reference signals to provide correlation results. The method then detects a primary synchronization signal (PSS) based on the correlation results.

Abstract: A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa field and shares an exponent field, thereby increasing the possible size of each distinct signed mantissa field by as much as one half the number of bits formerly employed to store a single distinct exponent field.

Abstract: A multicarrier transceiver is disclosed that includes a digital signal processor with a plurality of memory locations, a direct memory, an encoder module coupled to receive data from the FIFO buffers, a decoder module coupled to receive data from the FIFO buffers, a Fourier transform module configured to perform an inverse Fast Fourier transform for transmit operations and to perform Fast Fourier transform (FFT) operations for receive operations, a plurality of distributed modules including the encoder module, the decoder module and the Fourier transform module, each module configured with a memory port, each memory port coupled to a peripheral bus and the DMA bus, a plurality of memory ports coupled to each of the distributed modules, the plurality of memory ports coupled to a peripheral bus, and a plurality of point-to-point buses coupled to each of the distributed modules, the point-to-point bus configured to enable data flow and testing and provide a bypass capability for each of the distributed modules.

Abstract: A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa field and shares an exponent field, thereby increasing the possible size of each distinct signed mantissa field by as much as one half the number of bits formerly employed to store a single distinct exponent field.

Abstract: A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa field and shares an exponent field, thereby increasing the possible size of each distinct signed mantissa field by as much as one half the number of bits formerly employed to store a single distinct exponent field.

Abstract: A Fourier transform architecture and system for FFT and IFFT processing within multicarrier transceiver is disclosed that includes a programmable butterfly component, a memory and a programmable address generation unit. The architecture includes a butterfly component configured to perform a plurality of radix butterfly calculations, and a four bank memory configured to operate on sample data. The architecture further includes a programmable address generation unit coupled to the pipeline to enable the architecture to perform calculations independent of Fourier-based algorithms. A method for addressing memory banks for an FFT pipeline includes expressing an index in radix notation, computing a bank address for a bank memory, converting the bank address to a reduced size by ignoring one or more bits, and calculating the bank address within the reduced memory bank.

Abstract: A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa field and shares an exponent field, thereby increasing the possible size of each distinct signed mantissa field by as much as one half the number of bits formerly employed to store a single distinct exponent field.

Abstract: A Fourier transform architecture and system for FFT and IFFT processing within multicarrier transceiver is disclosed that includes a programmable butterfly component, a memory and a programmable address generation unit. The architecture includes a butterfly component configured to perform a plurality of radix butterfly calculations, and a four bank memory configured to operate on sample data. The architecture further includes a programmable address generation unit coupled to the pipeline to enable the architecture to perform calculations independent of Fourier-based algorithms. A method for addressing memory banks for an FFT pipeline includes expressing an index in radix notation, computing a bank address for a bank memory, converting the bank address to a reduced size by ignoring one or more bits, and calculating the bank address within the reduced memory bank.

Abstract: A multicarrier transceiver is disclosed that includes a digital signal processor with a plurality of memory locations, a direct memory, an encoder module coupled to receive data from the FIFO buffers, a decoder module coupled to receive data from the FIFO buffers, a Fourier transform module configured to perform an inverse Fast Fourier transform for transmit operations and to perform Fast Fourier transform (FFT) operations for receive operations, a plurality of distributed modules including the encoder module, the decoder module and the Fourier transform module, each module configured with a memory port, each memory port coupled to a peripheral bus and the DMA bus, a plurality of memory ports coupled to each of the distributed modules, the plurality of memory ports coupled to a peripheral bus, and a plurality of point-to-point buses coupled to each of the distributed modules, the point-to-point bus configured to enable data flow and testing and provide a bypass capability for each of the distributed modules.

Abstract: A method and apparatus for aligning a received echo signal. The method operates by determining a memory address pointer value that directs which transmit data is to be transmitted. The pointer is selected such that an appropriate delay is created, resulting in the associated received echo having a certain timing alignment within the received block of data. The method thus includes predetermining a pointer or pointer offset value; generating blocks of digital transmit data; transferring the transmit digital data to a converter using the determined pointer or pointer offset value; converting the transmit digital data to a transmit analog signal and transmitting the analog signal; sampling a received signal and forming blocks of received digital data, wherein the received signal includes a transmit echo; and wherein the pointer offset results in block alignment between the transmit echo from a transmit block and a receive block.