Abstract: A programmable packet processing system is disclosed wherein a lower speed processor is used to process higher speed data. The system comprises a plurality of packet processor “cores”, for serial connection one to another. Data packet arbitration is performed by each processor in sequence such that packets for processing by a processor are not passed on down the serial pipeline and those that are not for processing by a present processor are passed downstream. The pipeline also includes an ordering circuit for ensuring that processed packets are provided to an output of the pipeline in the order they are received.