Abstract: A clock may be generated having a predetermined unit interval. Received data may then be compared to the virtual clock to determine whether more than one data change occurs during a particular unit interval. If more than one data change occurs during a particular unit interval, the virtual clock may not correspond to the source clock. The virtual clock may then be incremented by a phase shift offset and the data analyzed again. When a phase shift virtual clock is identified that aligns with the data such that a plurality of data changes do not occur during a given unit interval, the embodiment may determine that a passing virtual clock may have been identified.

Abstract: A method and an apparatus for transmit phase select are disclosed. In one embodiment, the method includes selecting one or more phases out of a set of phases of a clock, transmitting a data pattern in each of the selected phases, and receiving the loop-back data pattern. The techniques described herein can be used in screening out defective high-speed serial interface as well as design validation of the interface.