Abstract: The present device comprises a power divider network, to which a signal to be amplified is applied, for distributing the power of the signal among several amplifying channels, one amplifier per amplifying channel for amplifying the power-divided signal, and a power combiner circuit for combining the amplified signals at the output of each channel into a single signal, the RF power desired at the output of the device determining the number of amplified signals to be combined, the amplifier of each channel comprising an integrated circuit including a controllable output transistor for deactivating the amplifier, the power combiner circuit comprising a quarter wave impedance transformer circuit for each channel connected to a common junction node coupled to the device output.

Abstract: The present device comprises a power divider network (1′), to which a signal (E) to be amplified is applied, for distributing the power of said signal among several amplifying channels, one amplifier (22) per amplifying channel for amplifying the power-divided signal, and a power combiner circuit (5) for combining the amplified signals at the output of each channel into a single signal, the RF power desired at the output of the device determining the number of amplified signals to be combined, the amplifier (22) of each channel comprising an integrated circuit including a controllable output transistor for deactivating the amplifier, the power combiner circuit (5) comprising a quarter wave impedance transformer circuit (51) for each channel connected to a common junction node coupled to the device output (S).

Abstract: Disclosed is a high-efficiency amplifying device wherein a control signal for a power-amplifying unit is produced from an input signal in a pre-amplification stage, resulting in a reduced disturbance output signal with a constant efficiency in the amplifying device.