Abstract: The present invention provides an automatic identification and tracking method and system for identifying whether a customer is a very important person (VIP), retrieving profile, demographical data and/or point of sale (POS) records of the customer, tracking location of the customer, and sending the retrieved profile and tracked location of the customer to mobile devices of staffs, therefore enhanced services and targeted advertisements can be provided to customers promptly and accurately.

Abstract: The present invention comprises capturing an image of a subject to be authenticated; a step of face verification; followed by the process steps of a scan line detection test, a specular reflection detection test, and a chromatic moment and color diversity feature analysis test in no particular order. The method requires a subject to present her face before a camera, which can be the built-in or peripheral camera of e.g. a mobile communication device or a mobile computing device. The method also requires displaying to the subject certain instructions and the real-time video feedback of the subject face on a display screen, which can be the built-in or peripheral display screen of the mobile communication device or mobile computing device.

Abstract: Systems, methods, and computer-readable storage media for constructing and using a model for tracking an object are disclosed. The model may be constructed from a plurality of images and a coordinate system defined with respect to the pedestal upon which the object is placed, where the plurality of images correspond to images of the object while the object is placed on a pedestal, and where the pedestal includes a plurality of markers. The model for tracking the object may be configured to provide information representative of a camera position during tracking of the object using a camera. Tracking the object using the model may include obtaining one or more images of the object using a camera, and determining a position of the camera relative to the object based on the model.

Abstract: The present invention employs a first step of stationary face recognition, followed by a facial expression test, a continuous movement tracking test, and a 3D perspective check to identify and authenticate a subject, prevent photo spoofing and facemask spoofing, and determining whether the subject is a living person. The method requires a subject to present her face before a camera, which can be the built-in or peripheral camera of a mobile communication device. The method also requires displaying to the subject certain instructions and the real-time video feedback of the subject face on a display screen, which can be the built-in or peripheral display screen of the mobile communication device or mobile computing device. The 3D perspective check uses a single camera to take two images of the subject's face for the calculating the stereoscopic view data of the subject's face.

Abstract: A computer implemented method for tracking a marker on a deformable surface in augmented reality (AR) applications, comprising: detecting image-key-points in a currently processed video frame of a video-captured scene; performing key-point-correspondence searching and matching the image-key-points with model-key-points are identified from an original image of the marker, comprising: calculating an key-point matching score for each image-key-point; applying a key-point matching score filter on the key-point matching scores; restricting the searching of the image-key-points in the currently processed video frame to within same mesh block determined in a previously processed video frame of the captured video frames; and applying adaptive thresholds on the key-point matching scores in determining successful matches of the image-key-points; performing motion detection of the marker in the video-captured scene and halting the application of the key-point matching score filter and suspending the restriction on the i

Abstract: A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.

Abstract: A computer implemented method for tracking a marker on a deformable surface in augmented reality (AR) applications, comprising: detecting image-key-points in a currently processed video frame of a video-captured scene; performing key-point-correspondence searching and matching the image-key-points with model-key-points are identified from an original image of the marker, comprising: calculating an key-point matching score for each image-key-point; applying a key-point matching score filter on the key-point matching scores; restricting the searching of the image-key-points in the currently processed video frame to within same mesh block determined in a previously processed video frame of the captured video frames; and applying adaptive thresholds on the key-point matching scores in determining successful matches of the image-key-points; performing motion detection of the marker in the video-captured scene and halting the application of the key-point matching score filter and suspending the restriction on the i

Abstract: A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.

Abstract: A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.

Abstract: Heat accumulated inside the human body can affect performance and may also lead to heat stroke, hyperthermia and even death. A method and system for performance enhancing body cooling with the use of thermoelectric cooling plate for performance enhancement and prevention of heat stress/heat stroke/hyperthermia is described. The system targets the glabrous skins in the palm for optimal heat extraction and the portable device allows continuous cooling for longer duration. A heavy-duty version of the device using multiple thermoelectric cooling plates for cooling of body under extreme heat conditions such as inside a tank or armored personnel vehicle (APV) for military applications is also described.

Abstract: In a broadcast receiver for receiving a digital broadcast signal that carries time division multiplexed content programs or channels configured for power saving modes, the tuner, the ADC, the sub-modules within demodulator core, and the decoder are partitioned into multiple power domains forming a signal data processing pipeline with stages that are corresponding to the power domains and according to the boundaries of the data processing steps. During burst timeslot, only the power domain that is processing the signal data is turned on. Once the processing is completed the power domain is turned off. The power domains are turned off during non-burst timeslot. The ADCs and the first power domain are turned on one timeslot prior the beginning of the next burst timeslot. Therefore, the receiver can simply disregard any residual data in the processing pipeline from the last burst cycle and data flushing is not necessary.

Abstract: A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.

Abstract: Data is transferred on a first port during a current cycle until a predetermined number of bytes less an overshoot value for the first port has been transferred on the first port. The transfer of data continues on the first port during the current cycle until a complete packet has been transferred on the first port. An overshoot value for the first port is updated based on the number of bytes transferred on the first port. In one embodiment, a pair of ports are sequentially selected from a plurality of pairs of ports. The pair of ports comprises a port connected to a first interface and a port connected to a second interface. Data is transferred on the port connected to the first interface during a current cycle. Data is transferred on the port connected to the second interface during the current cycle.

Abstract: A method and apparatus for processing channelized and unchannelized data within a signal are described. In one embodiment, a method comprises receiving in a network element, data packets within a number of channels, wherein each of the number of channels are channelized or unchannelized, processing, in a protocol engine within the network element, the data packets within the number of channels that are channelized, and processing, in the protocol engine within the network element, the data packets within the number of channels that are unchannelized.

Abstract: A system comprising a central processing unit (102) for use in executing RISC instructions and a hardware unit (100) associated with the central processing unit (102), is disclosed. The hardware unit (100) is configured for translating stack-based instructions into RISC instructions for execution by the central processing unit (102). The translation is performed using a programmable lookup table.

Abstract: A method and apparatus for disabling a data interface between network element data processing units is described. In one embodiment, the method includes transmitting data frames over a data connection through an interface of a first network element data processing unit to a second network element data processing unit, disabling the interface, receiving an interface disable signal, completing transmission of data frames currently being transmitted, upon receiving an interface disable signal, disabling the interface, the disabling not causing data loss, receiving acknowledgements over the data connection, and enabling the data connection after receiving a number of acknowledgements.

Abstract: A method and apparatus for processing data packets of differing protocols across different channels within signals are described. In an embodiment, a method includes receiving at least one signal, wherein the at least one signal includes a number of channels such that each of the number of channels can include different protocols and different configurations for the different protocols. The method also includes processing data packets in each of the number of channels in a predefined order.

Abstract: A bit-synchronous HDLC engine that processes data in parallel, during a single clock cycle is provided. The HDLC engine of the invention is significantly faster than previous bit-synchronous HDLC engines and, thus, is capable of handling greater bandwidths.

Abstract: A method and apparatus for processing data packets of differing protocols across different data channels and control channels within signals are described. In an embodiment, a method includes receiving at least one data signal, wherein the at least one data signal includes a number of channels. The number of channels includes data channels and control channels, such that each of the data channels can include different protocols and different configurations for the different protocols and such that the control channels includes control data for controlling the at least one data signal. Additionally, the method includes processing data packets in each of the number of channels in a predefined order.