Abstract: A digital filter for processing at least one input signal is described. The digital filter includes at least two filter parts that are separately formed from each other. The at least two filter parts are configured to process the at least one input signal in parallel which is received by the digital filter. A first filter part of the at least two filter parts is implemented in a first chip. A second filter part of the at least two filter parts is implemented in a second chip. Further, a measurement instrument is described.

Abstract: A signal analyzer for analyzing an input signal comprises at least one input for receiving the input signal, at least one acquisition unit for acquiring data assigned to the input signal, an acquisition memory for storing the acquired data, the acquisition memory being adapted to store data in at least one ring buffer, and an acquisition memory controller to control at least one of writing the acquired data in the acquisition memory and reading the acquired data from the acquisition memory. The acquisition memory controller comprises a data read module for reading data of the at least one ring buffer. The acquisition memory controller comprises a copy write module which taps data read by the data read module. The acquisition memory comprises an additional memory section. The copy write module is configured to write the data tapped into the additional memory section. Further, a method of processing data from an input signal is described.

Abstract: A signal acquisition circuit for acquiring data of an input signal comprising at least n acquisition units, wherein n is integer greater than one, the n acquisition units comprising k inputs, wherein k is integer greater than one, and wherein at least two inputs are assigned to one channel and the corresponding acquisition units run time interleaved, and at least one trigger unit, wherein the number 1 of the at least one trigger unit is integer and wherein 1 is smaller than k. Further, a single-housed device as well as a method of acquiring data of an input signal are described.

Abstract: An acquisition system includes a first acquisition and quantizer unit, a second acquisition and quantizer unit as well as a trigger unit. The first and second acquisition and quantizer units are configured to receive a respective interleaved digitized input signal, to acquire the respective interleaved digitized input signal, to quantize the respective interleaved digitized input signal, and to output a respective quantized interleaved digitized input signal. The trigger unit is configured to receive the respective quantized interleaved digitized input signals from the first and second acquisition and quantizer units. The trigger unit is further configured to de-interleave the respective quantized interleaved digitized input signals. The trigger unit is configured to generate a de-interleaved quantized digitized input signal. The trigger unit is also configured to detect an event in the de-interleaved quantized digitized input signal. Further, a method of acquiring a high bandwidth input signal is described.

Abstract: A signal analyzer for analyzing an input signal comprises at least one input for receiving the input signal, at least one acquisition unit for acquiring data assigned to the input signal, an acquisition memory for storing the acquired data, the acquisition memory being adapted to store data in at least one ring buffer, and an acquisition memory controller to control at least one of writing the acquired data in the acquisition memory and reading the acquired data from the acquisition memory. The acquisition memory controller comprises a data read module for reading data of the at least one ring buffer. The acquisition memory controller comprises a copy write module which taps data read by the data read module. The acquisition memory comprises an additional memory section. The copy write module is configured to write the data tapped into the additional memory section. Further, a method of processing data from an input signal is described.

Abstract: A signal acquisition circuit for acquiring data of an input signal comprising at least n acquisition units, wherein n is integer greater than one, the n acquisition units comprising k inputs, wherein k is integer greater than one, and wherein at least two inputs are assigned to one channel and the corresponding acquisition units run time interleaved, and at least one trigger unit, wherein the number 1 of the at least one trigger unit is integer and wherein 1 is smaller than k. Further, a single-housed device as well as a method of acquiring data of an input signal are described.

Abstract: An interleaved acquisition system for acquiring a high bandwidth input signal, comprising a first acquisition and quantizer unit, a second acquisition and quantizer unit as well as a trigger unit. The first and second acquisition and quantizer units are configured to receive a respective interleaved digitized input signal, to acquire the respective interleaved digitized input signal, to quantize the respective interleaved digitized input signal, and to output a respective quantized interleaved digitized input signal. The trigger unit is configured to receive the respective quantized interleaved digitized input signals from the first and second acquisition and quantizer units. The trigger unit is further configured to de-interleave the respective quantized interleaved digitized input signals. The trigger unit is configured to generate a de-interleaved quantized digitized input signal. The trigger unit is also configured to detect an event in the de-interleaved quantized digitized input signal.