Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, and forming a mask over the device structure including within each of the plurality of trenches and over a top surface of the device structure. The method may further include removing the mask from within the trenches, wherein the mask remains along the top surface of the device structure, and implanting the device structure to form a treated layer along a bottom of the trenches. In some embodiments, the method may further include forming a gate oxide layer along a sidewall of each of the trenches and along the bottom of the trenches, wherein a thickness of the oxide along the bottom of the trenches is greater than a thickness of the oxide along the sidewall of each of the trenches.

Abstract: A method for performing an ion implantation process including providing a hardmask layer disposed atop a substrate, providing a photoresist layer disposed atop the hardmask layer and defining a pattern exposing a portion of the hardmask layer, performing a room temperature ion implantation process wherein an ion beam formed of an ionized first dopant species is directed onto the exposed portion of the hardmask layer to make the exposed portion more susceptible to ion etching or wet etching, performing an etching process wherein the exposed portion of the hardmask layer is etched away to expose an underlying portion of the substrate, and performing a high energy, hot ion implantation process wherein an ion beam formed of a ionized second dopant species is directed onto the exposed portion of the substrate.

Abstract: A method of forming a gate of a planar metal oxide semiconductor field effect transistor (MOSFET) reduces gate-drain capacitance. The method may include forming a first gate dielectric portion of the planar MOSFET with a first thickness that is configured to reduce the gate-drain capacitance of the planar MOSFET, forming a second gate dielectric portion of the planar MOSFET on the substrate with a second thickness less than the first thickness, and forming the gate of the planar MOSFET on the first gate dielectric portion and the second gate dielectric portion on the substrate.

Abstract: A method of forming a gate of a planar metal oxide semiconductor field effect transistor (MOSFET) reduces gate-drain capacitance. The method may include forming a first gate dielectric portion of the planar MOSFET with a first thickness that is configured to reduce the gate-drain capacitance of the planar MOSFET, forming a second gate dielectric portion of the planar MOSFET on the substrate with a second thickness less than the first thickness, and forming the gate of the planar MOSFET on the first gate dielectric portion and the second gate dielectric portion on the substrate.

Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, and forming a mask over the device structure including within each of the plurality of trenches and over a top surface of the device structure. The method may further include removing the mask from within the trenches, wherein the mask remains along the top surface of the device structure, and implanting the device structure to form a treated layer along a bottom of the trenches. In some embodiments, the method may further include forming a gate oxide layer along a sidewall of each of the trenches and along the bottom of the trenches, wherein a thickness of the oxide along the bottom of the trenches is greater than a thickness of the oxide along the sidewall of each of the trenches.

Abstract: A method for performing an ion implantation process including providing a hardmask layer disposed atop a substrate, providing a photoresist layer disposed atop the hardmask layer and defining a pattern exposing a portion of the hardmask layer, performing a room temperature ion implantation process wherein an ion beam formed of an ionized first dopant species is directed onto the exposed portion of the hardmask layer to make the exposed portion more susceptible to ion etching or wet etching, performing an etching process wherein the exposed portion of the hardmask layer is etched away to expose an underlying portion of the substrate, and performing a high energy, hot ion implantation process wherein an ion beam formed of a ionized second dopant species is directed onto the exposed portion of the substrate.