Abstract: The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

Abstract: Disclosed is reinforced via farm interconnect structure for an integrated circuit chip that minimizes delamination caused by tensile stresses applied to the chip through lead-free C4 connections during thermal cycling. The reinforced via farm interconnect structure includes a plurality of vias electrically connecting metal wires within different wiring levels and, for reinforcement, further incorporates dielectric columns into the lower metal wire so that the areas around the metal-to-metal interface between the vias and the lower metal wire contain a relatively strong dielectric-to-dielectric interface. The reinforced via farm interconnect structure can be located in an area of the chip at risk for delamination and, for added strength, can have a reduced via density relative to conventional via farm interconnect structures located elsewhere on the chip.

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

Abstract: The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.

Abstract: A MEMS structure and methods of manufacture. The method includes forming a sacrificial metal layer at a same level as a wiring layer, in a first dielectric material. The method further includes forming a metal switch at a same level as another wiring layer, in a second dielectric material. The method further includes providing at least one vent to expose the sacrificial metal layer. The method further includes removing the sacrificial metal layer to form a planar cavity, suspending the metal switch. The method further includes capping the at least one vent to hermetically seal the planar cavity.

Abstract: Disclosed is an improved integrated circuit wiring structure configured to prevent migration of wiring metal ions (e.g., copper (Cu+) ions in the case of a copper interconnect scheme) onto the surface of an interlayer dielectric material at an interface between the interlayer dielectric material and an insulating cap layer. Specifically, the top surfaces of wires and the top surface of a dielectric layer within which the wires sit are not co-planar. Thus, the interfaces between the wires and an insulating cap layer and between the dielectric layer and the same insulating cap layer are also not co-planar. Such a configuration physically prevents migration of wiring metal ions from the top surface of the wires onto the top surface of the dielectric layer at the interface between the dielectric layer and cap layer and, thereby prevents time dependent dielectric breakdown (TDDB) and eventual device failure. Also disclosed herein are embodiments of a method of a forming such an integrated circuit wiring structure.

Abstract: Integrated MEMS switches, design structures and methods of fabricating such switches are provided. The method includes forming at least one tab of sacrificial material on a side of a switching device which is embedded in the sacrificial material. The method further includes stripping the sacrificial material through at least one opening formed on the at least one tab which is on the side of the switching device, and sealing the at least one opening with a capping material.

Abstract: Methods of avoiding chemical mechanical polish (CMP) edge erosion and a related wafer are disclosed. In one embodiment, the method includes providing a wafer; forming a first material across the wafer; forming a second material at an outer edge region of the wafer, leaving a central region of the wafer devoid of the second material; and performing chemical mechanical polishing (CMP) on the wafer. The second material diminishes CMP edge erosion.

Abstract: Vertical integrated MEMS switches, design structures and methods of fabricating such vertical switches is provided herein. The method of manufacturing a MEMS switch, includes forming at least two vertically extending vias in a wafer and filling the at least two vertically extending vias with a metal to form at least two vertically extending wires. The method further includes opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

Abstract: A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure.

Abstract: Methods of avoiding chemical mechanical polish (CMP) edge erosion and a related wafer are disclosed. In one embodiment, the method includes providing a wafer; forming a first material across the wafer; forming a second material at an outer edge region of the wafer, leaving a central region of the wafer devoid of the second material; and performing chemical mechanical polishing (CMP) on the wafer. The second material diminishes CMP edge erosion.

Abstract: Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process.