Abstract: A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure. A corresponding apparatus and design structure are also described.

Abstract: A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure. A corresponding apparatus and design structure are also described.

Abstract: A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure.

Abstract: A structure and method of forming the structure. At least one copper wire is formed within a first dielectric layer of a substrate. The top surface of each copper wire and of the first dielectric layer are essentially coplanar. A recess is formed in the first dielectric layer from the top surface of each copper wire to a recess depth less than a thickness of each copper wire within the first dielectric layer such that the recess surrounds a perimeter surface of each copper wire. A capping layer, which is a copper diffusion barrier, is formed in the recess and on the top surface of each copper wire and on the first dielectric layer. A second dielectric layer is formed on the capping layer. The recess depth has a magnitude sufficient to prevent a lateral fail of the capping layer during packaging and/or operation of the substrate.

Abstract: Electronic devices and design structures of electronic devices containing metal silicide layers. The devices include: a thin silicide layer between two dielectric layers, at least one metal wire abutting a less than whole region of the silicide layer and in electrical contact with the silicide layer.

Abstract: Methods of forming metal silicide layers. The methods include: forming a silicon-rich layer between dielectric layers; contacting the silicon-rich layer with a metal layer and heating the silicon rich-layer and the metal layer to diffuse metal atoms from the metal layer into the silicon layer to form a metal silicide layer.

Abstract: Methods of forming metal silicide layers. The methods include: forming a silicon-rich layer between dielectric layers; contacting the silicon-rich layer with a metal layer and heating the silicon rich-layer and the metal layer to diffuse metal atoms from the metal layer into the silicon layer to form a metal silicide layer.

Abstract: Electronic devices and design structures of electronic devices containing metal silicide layers. The devices include: a thin silicide layer between two dielectric layers, at least one metal wire abutting a less than whole region of the silicide layer and in electrical contact with the silicide layer.

Abstract: A structure and method of forming the structure. At least one copper wire is formed within a first dielectric layer of a substrate. The top surface of each copper wire and of the first dielectric layer are essentially coplanar. A recess is formed in the first dielectric layer from the top surface of each copper wire to a recess depth less than a thickness of each copper wire within the first dielectric layer such that the recess surrounds a perimeter surface of each copper wire. A capping layer, which is a copper diffusion barrier, is formed in the recess and on the top surface of each copper wire and on the first dielectric layer. A second dielectric layer is formed on the capping layer. The recess depth has a magnitude sufficient to prevent a lateral fail of the capping layer during packaging and/or operation of the substrate.

Abstract: A method for forming a vertical natural capacitor in an integrated circuit is disclosed. In one embodiment, the method includes forming a first set of concentric conductive annular structures in a first metal layer of an integrated circuit. The first set includes a first electrode and a second electrode. The method further includes forming a second set of concentric conductive annular structures in a second metal layer of the integrated circuit, the second set being substantially axially concentric with the first set. The second set also includes a first electrode and a second electrode. The method includes coupling, using conductive vias, the first electrode of the first set to the first electrode of the second set, and the second electrode of the first set to the second electrode of the second set.