Abstract: A multi-service switch for a telecommunications network (10) is provided. A system bus (13) has an ingress portion (14) and an egress portion (16). The system bus (13) is operable to carry data in a plurality of time slots. A system bus control (11) comprises a head-of-bus control (12) having an output. The output of the head-of-bus control is coupled to the ingress portion (14) of the system bus (13). The system bus control (11) also comprises a tail-of-bus control (15) coupled to the head-of-bus control (12). The tail-of-bus control (15) has an input coupled to the egress portion (16) of the system bus (13). A plurality of interface modules (28.sub.1 through 28.sub.n) each have an input and an output. The input of each interface module (28.sub.1 through 28.sub.n) is coupled to the egress portion (16) of the system bus (13), and the output of each interface module is coupled to the ingress portion (14) of the system bus (13). An ingress/egress bridge (18) has an input and an output.

Abstract: A buffered crosspoint matrix (20) of an asynchronous transfer mode switch (10) includes a plurality of switching elements (38) for receiving and switching segments containing asynchronous transfer mode cells. Each switching element (38) receives segments at a plurality of multicast/routing elements (52). Each multicast/routing element generates insert enable signals for each segment to route segments to selected crosspoints (58) of a plurality of vertical bar elements (54). Each vertical bar element (54) includes a plurality of queuing systems (90) for receiving and storing segments within an associated common buffer area (94). Segments are prioritized according to class of service and segment locations within the common buffer area (94) are stored in subqueues (104) according to their corresponding class of service. Each queuing system (90) performs a first phase contention resolution tournament to determine an oldest segment of those segments at the head of the subqueue (104) list.

Abstract: A buffered crosspoint matrix (20) of an asynchronous transfer mode switch (10) includes a plurality of switching elements (38) for receiving and switching segments containing asynchronous transfer mode cells. Each switching element (38) receives segments at a plurality of multicast/routing elements (52). Each multicast/routing element generates insert enable signals for each segment to route segments to selected crosspoints (58) of a plurality of vertical bar elements (54). Each vertical bar element (54) includes a plurality of queuing systems (90) for receiving and storing segments within an associated common buffer area (94). Segments are prioritized according to class of service and segment locations within the common buffer area (94) are stored in subqueues (104) according to their corresponding class of service. Each queuing system (90) performs a first phase contention resolution tournament to determine an oldest segment of those segments at the head of the subqueue (104) list.

Abstract: A multi-service switch for a telecommunications network (10) is provided. A system bus (13) has an ingress portion (14) and an egress portion (16). The system bus (13) is operable to carry data in a plurality of time slots. A system bus control (11) comprises a head-of-bus control (12) having an output. The output of the head-of-bus control is coupled to the ingress portion (14) of the system bus (13). The system bus control (11) also comprises a tail-of-bus control (15) coupled to the head-of-bus control (12). The tail-of-bus control (15) has an input coupled to the egress portion (16) of the system bus (13). A plurality of interface modules (28.sub.1 through 28.sub.n) each have an input and an output. The input of each interface module (28.sub.1 through 28.sub.n) is coupled to the egress portion (16) of the system bus (13), and the output of each interface module is coupled to the ingress portion (14) of the system bus (13). An ingress/egress bridge (18) has an input and an output.

Abstract: Three data formats for telecommunication networks are provided. One format is an asynchronous packet bus overlay datagram format (122) constructed to include an internal datagram header (140) and a datagram payload (141) concatenated with the internal datagram header. The internal datagram header comprises a destination address (146), a weighted age (152), and a source address (14). A second format is a wideband bus overlay format (126) comprising three header octets and a plurality of payload octets such that the data is formatted into one of a plurality of industry standard isochronous wideband data formats. A third format is a narrow band bus overlay format (124) comprising a plurality of signaling octets, a plurality of octets concatenated with the first plurality of signaling octets to hold data, and a common system multiframe structure.

Abstract: A bus arbitration method for telecommunications switching is provided that receives a plurality of requests of a plurality of priorities for an available asynchronous bus time slot, wherein each request has a weighted age. The plurality of requests are ordered according to the weighted age of each request and access to the bus time slot is granted to a request having the highest weighted age. Further, a bus arbitration method for telecommunications switching is provided that generates a plurality of requests of a plurality of priorities for each of a plurality of packets needing an available bus time slot. An amount of time during which each request is pending is measured. The plurality of requests for the available asynchronous bus time slot are sent to a centralized asynchronous slot arbiter operable to grant access to one of the plurality of packets corresponding to a request having a highest weighted age.

Abstract: A method and apparatus for a high speed asynchronous transfer mode switch is provided which includes an input buffer circuit coupled to communication lines for receiving and temporarily storing packets from the communication lines, a switch comprising one or more planes and output circuitry for coupling the switch outputs to respective communication lines. The switch is comprised of a plurality of switching elements, each of which include a sorter for ranking packets responsive to addresses associated with the packets, compare circuitry for receiving the ranked packets from the sorter and passing up to a predetermined number of packets having the same address, and routing circuitry for routing the packets passed by the compare circuitry responsive to the associated addresses. After a packet is successfully transferred through the switch, an acknowledge signal is returned to the sending input buffer circuit.

Abstract: A switching system (10) configured in a ring topology (14) is disclosed. The system (10) causes one or more 125 microsecond isochronous frames (20) to circulate in the ring (14) at any given instant in time. A delay circuit (22) temporarily saves an oldest one of the isochronous frames (20) until a youngest one of the isochronous frames (20) has completed its transmission. Consequently, an integral number of isochronous frames (20) circulate in ring (14). The isochronous frame (20) is partitioned to support a random access tunnel channel (26) and a plurality of independently controlled cells (28), which provide a variety of deterministic access services. Each cell (28) contains a control field (30) that contains sufficient information to specify the type of switching service provided by the cell (28) and various service parameters. A time multiplexer (42) separates the tunnel channel (26) from the cells (28).

Abstract: A continuity check tone detector for use with a digital telecommunication system and being designed for detecting continuous tones on voice transmission paths temporarily established between a digital tone generator and the detector across a switching network under control of a switch control unit. The tone detector includes detector interfaces receiving serial tone information from each transmission path in order to derive a digital tone sample and serial control information from the switch control unit in order to convert the same into timing and control signals. A digital signal processor under control of said timing and control signals linearizes and filters received tone samples, measures the power thereof, and supplies corresponding output data. A control processor receives this output data for evaluating the same with respect to individually set power level and predetermined duration for determining the presence of a continuous test tone.