Patents by Inventor Fen F. Jamin
Fen F. Jamin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7214623Abstract: Disclosed herein are a system and method of polishing a layer of a substrate. The disclosed method includes providing a polishing apparatus adapted to impart relative movement between a polishing pad and a substrate having a first layer to be polished; providing a liquid medium having a pH between 4 and 11 to an interface between the substrate and the polishing pad, the liquid medium including a pH controlling substance including at least one of an acid and a base, a carbonate and a stabilizer additive comprising at least one selected from the group consisting of amino acids and polyacrylic acid; and moving at least one of the substrate and the polishing pad relative to the other to polish the layer of the substrate.Type: GrantFiled: October 13, 2003Date of Patent: May 8, 2007Assignee: International Business Machines CorporationInventors: Donald J. Delehanty, James W. Hannah, Daniel M. Heenan, Fen F. Jamin, Laertis Economikos
-
Patent number: 7064064Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.Type: GrantFiled: February 16, 2005Date of Patent: June 20, 2006Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Timothy J. Dalton, Kenneth M. Davis, Chao-Kun Hu, Fen F. Jamin, Steffen K. Kaldor, Mahadevaiyer Krishnan, Kaushik Kumar, Michael F. Lofaro, Sandra G. Malhotra, Chandrasekhar Narayan, David L. Rath, Judith M. Rubino, Katherine L. Saenger, Andrew H. Simon, Sean P. E. Smith, Wei-tsu Tseng
-
Patent number: 7041600Abstract: A method of planarization allows for the use of chemical mechanical polishing (CMP) in starting structures having films not generally suitable for CMP processes. Two material layers are formed over a starting structure, and the upper layer is planarized in a CMP process. A nonselective etch is then used to transfer the planar topography to the lower level.Type: GrantFiled: June 30, 2003Date of Patent: May 9, 2006Assignee: International Business Machines CorporationInventors: Omer Dokumaci, Bruce Doris, David Horak, Fen F. Jamin
-
Patent number: 6975032Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.Type: GrantFiled: December 16, 2002Date of Patent: December 13, 2005Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Timothy J. Dalton, Kenneth M. Davis, Chao-Kun Hu, Fen F. Jamin, Steffen K. Kaldor, Mahadevaiyer Krishnan, Kaushik Kumar, Michael F. Lofaro, Sandra G. Malhotra, Chandrasekhar Narayan, David L. Rath, Judith M. Rubino, Katherine L. Saenger, Andrew H. Simon, Sean P. E. Smith, Wei-tsu Tseng
-
Publication number: 20040266195Abstract: A method of planarization allows for the use of chemical mechanical polishing (CMP) in starting structures having films not generally suitable for CMP processes. Two material layers are formed over a starting structure, and the upper layer is planarized in a CMP process. A nonselective etch is then used to transfer the planar topography to the lower level.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Omer Dokumaci, Bruce Doris, David Horak, Fen F. Jamin
-
Patent number: 6780695Abstract: A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area.Type: GrantFiled: April 18, 2003Date of Patent: August 24, 2004Assignee: International Business Machines CorporationInventors: Huajie Chen, Seshadri Subbanna, Basanth Jagannathan, Gregory G. Freeman, David C. Ahlgren, David Angell, Kathryn T. Schonenberg, Kenneth J. Stein, Fen F. Jamin
-
Patent number: 6764922Abstract: An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.Type: GrantFiled: November 7, 2003Date of Patent: July 20, 2004Assignee: International Business Machines CorporationInventors: Klaus D. Beyer, Fen F. Jamin, Patrick R. Varekamp
-
Publication number: 20040113279Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.Type: ApplicationFiled: December 16, 2002Publication date: June 17, 2004Applicant: International Business Machines CorporationInventors: Shyng-Tsong Chen, Timothy J. Dalton, Kenneth M. Davis, Chao-Kun Hu, Fen F. Jamin, Steffen K. Kaldor, Mahadevaiyer Krishnan, Kaushik Kumar, Michael F. Lofaro, Sandra G. Malhotra, Chandrasekhar Narayan, David L. Rath, Judith M. Rubino, Katherine L. Saenger, Andrew H. Simon, Sean P.E. Smith, Wei-tsu Tseng
-
Publication number: 20040106267Abstract: An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.Type: ApplicationFiled: November 7, 2003Publication date: June 3, 2004Applicant: International Business Machines CorporationInventors: Klaus D. Beyer, Fen F. Jamin, Patrick R. Varekamp
-
Patent number: 6709951Abstract: An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.Type: GrantFiled: September 18, 2002Date of Patent: March 23, 2004Assignee: International Business Machines CorporationInventors: Klaus D. Beyer, Fen F. Jamin, Patrick R. Varekamp
-
Publication number: 20030015736Abstract: An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.Type: ApplicationFiled: September 18, 2002Publication date: January 23, 2003Inventors: Klaus D. Beyer, Fen F. Jamin, Patrick R. Varekamp
-
Patent number: 6498383Abstract: An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.Type: GrantFiled: May 23, 2001Date of Patent: December 24, 2002Assignee: International Business Machines CorporationInventors: Klaus D. Beyer, Fen F. Jamin, Patrick R. Varekamp
-
Publication number: 20020177270Abstract: An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.Type: ApplicationFiled: May 23, 2001Publication date: November 28, 2002Applicant: International Business Machines CorporationInventors: Klaus D. Beyer, Fen F. Jamin, Patrick R. Varekamp
-
Patent number: 6365328Abstract: A method for forming an electrode. The method includes forming a conductive plug through a first dielectric layer. The plug extends from an upper surface of the first dielectric layer to a contact region in a semiconductor substrate. The electrode is formed photolithographically, misalignment of a mask registration in the photolithography resulting in exposing surface portions of the barrier contact. A second dielectric layer is deposited over the first dielectric layer, over side portions and top portions of the formed electrode, and over the exposed portions of barrier contact. A sacrificial material is provided on portions of the second dielectric layer disposed on lower sides of the, electrode, on portions of the second dielectric layer disposed on the first dielectric layer, and on said exposed portions of the barrier contact while exposing portions of the second dielectric layer on the top portions and upper side portions of the formed electrode.Type: GrantFiled: March 10, 2000Date of Patent: April 2, 2002Assignees: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Hua Shen, David Kotecki, Satish Athavale, Jenny Lian, Laertis Economikos, Fen F. Jamin, Gerhard Kunkel, Nirmal Chaudhary