Patents by Inventor Fen Yu

Fen Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240413032
    Abstract: A semiconductor package includes an insulation layer provided between a molding compound and an electromagnetic interface (EMI) layer. The insulation layer covers an exposed portion of a bond wire that extends beyond a top surface of the molding compound due to a Z-height reduction of the molding compound. The insulation layer prevents a short from occurring between the bond wire and the EMI layer.
    Type: Application
    Filed: July 31, 2023
    Publication date: December 12, 2024
    Inventors: Shaopeng Dong, Fen Yu, Weng Khoon Mong
  • Publication number: 20240397735
    Abstract: A memory device includes a substrate, a controller die attached to the substrate, and a memory die stack. The memory die stack includes a first silicon die having a first contact pad surface and a bottom surface attached to the substrate. The memory die stack includes a second silicon die stacked on the first silicon die, the second silicon die including a second contact pad surface. An overhang portion of the second silicon die extends beyond the first silicon die. The memory die stack includes a printed support structure attached to the substrate, the printed support structure supporting the overhang portion of the second silicon die, and one or more bond wires that electrically connect the first and second contact pad surfaces to the substrate, thereby electrically connecting the first and second silicon dies to the controller die by way of the substrate.
    Type: Application
    Filed: August 11, 2023
    Publication date: November 28, 2024
    Inventors: Shujun Zheng, Jason Xiao, Youhua Xu, Yvonne Ming, Jiun Dong Loeh, Shino Jian, Fen Yu
  • Patent number: 12154860
    Abstract: A method of forming a semiconductor device includes forming vertical contact fingers in a substrate having side portions that are flexible. Contact fingers are formed near one or more edges of the flexible side portions of the substrate. After semiconductor dies are mounted to and electrically coupled to the substrate, the semiconductor device may be encapsulated by placing the device in a mold chase including upper and lower mold plates. The lower mold plate is sized smaller than the substrate so that the flexible side portions of the substrate including the contact fingers fold vertically upward to fit within the mold.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: November 26, 2024
    Assignee: Sandisk Technologies, Inc.
    Inventors: Zhongli Ji, Ning Ye, Chin-Tien Chiu, Fen Yu
  • Publication number: 20240332156
    Abstract: A thickness of a signal trace on a printed circuit board (PCB) or a substrate is increased by intentionally forming a solder bridge on a surface of the signal trace during a reflow process in which a flip chip die or other computing component is mounted to the PCB or the substrate. Specifically, adjacent interconnects of the flip chip die are coupled to the same signal trace on the PCB or the substrate. During the reflow process, solder associated with each interconnect flows into a space or area defined by the adjacent interconnects and forms a solder bridge within the space, thereby increasing a thickness of the signal trace.
    Type: Application
    Filed: July 24, 2023
    Publication date: October 3, 2024
    Inventors: Rui Yuan, Zengyu Zhou, Yihao Chen, Fen Yu, Paul Qu
  • Patent number: 12027497
    Abstract: A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The first stack of memory dies includes a first substack of staggered memory dies offset with respect to each other in a first direction and a second substack of staggered memory dies offset with respect to each other in the first direction and positioned above the first substack. The second stack of memory dies includes a third substack of staggered memory dies offset with respect to each other in a second direction and a fourth substack of staggered memory dies offset with respect to each other in the second direction and positioned above the third substack. The top memory die of the first substack and a memory die positioned below the top memory die of the third substack are at least partially coplanar.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: July 2, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Haiyue Shen, Fen Yu, Hope Chiu, Donghua Wu, Hua Tan, Xinyu Wang, Shenghua Huang
  • Patent number: 11810896
    Abstract: A method and apparatus for substrate component layout and bonding for increased package capacity. According to certain embodiments, a wire-bonding finger strip is disposed between a flip-chip die and a NAND die stack to reduce a keep out zone (KOZ) required for an underfill material dispensed beneath the flip-chip die. To further inhibit the flow of the underfill material and further reduce the KOZ, a solder mask may be placed adjacent to the flip-chip. According to certain embodiments, there may be at least three sides of the flip-chip that may have such an adjacent solder mask placement. The three sides of the flip-chip according to such embodiments may be those non-adjacent to the wire-bonding finger strip.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: November 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jiandi Du, Zengyu Zhou, Rui Yuan, Fen Yu, Hope Chiu
  • Patent number: 11784135
    Abstract: A semiconductor device has shielding to prevent transmission and/or reception of EMI and/or RFI radiation. The semiconductor device comprises a substrate including grounded contact pads around a periphery of the substrate, exposed at one or more edges of the substrate. A bump made of gold or other non-oxidizing conductive material may be formed on the contact pads, for example using ultrasonic welding to remove an oxidation layer between the contact pads and the conductive bumps. The conductive bumps electrically couple to a conductive coating applied around the periphery of the semiconductor device.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: October 10, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jiandi Du, Binbin Zheng, Rui Guo, Chin-Tien Chiu, Zengyu Zhou, Fen Yu
  • Publication number: 20230299034
    Abstract: A semiconductor device package includes a semiconductor die including bond pads and an underfill inlet side, a substrate including a first metal layer and lower metal layers underneath the first metal layer, a plurality of metal contacts and trace segment lines disposed in the first metal layer, and a plurality of solder bump rows. Each of the solder bump rows is oriented substantially parallel to the inlet side of the semiconductor die and electrically connects bond pads of the semiconductor die with corresponding metal contacts in the first metal layer of the substrate. Each of the trace segment lines is oriented substantially parallel to the inlet side of the semiconductor die, is electrically coupled to a respective solder bump row of the plurality of solder bump rows, and includes trace segments disposed in the first metal layer and trace segments disposed in one or more of the lower metal layers.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Yihao Chen, Tim Huang, Zengyu Zhou, Rui Yuan, Fen Yu, Hope Chiu
  • Publication number: 20230246000
    Abstract: A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The first stack of memory dies includes a first substack of staggered memory dies offset with respect to each other in a first direction and a second substack of staggered memory dies offset with respect to each other in the first direction and positioned above the first substack. The second stack of memory dies includes a third substack of staggered memory dies offset with respect to each other in a second direction and a fourth substack of staggered memory dies offset with respect to each other in the second direction and positioned above the third substack. The top memory die of the first substack and a memory die positioned below the top memory die of the third substack are at least partially coplanar.
    Type: Application
    Filed: February 1, 2022
    Publication date: August 3, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Haiyue Shen, Fen Yu, Hope Chiu, Donghua Wu, Hua Tan, Xinyu Wang, Shenghua Huang
  • Publication number: 20220406726
    Abstract: A semiconductor device has shielding to prevent transmission and/or reception of EMI and/or RFI radiation. The semiconductor device comprises a substrate including grounded contact pads around a periphery of the substrate, exposed at one or more edges of the substrate. A bump made of gold or other non-oxidizing conductive material may be formed on the contact pads, for example using ultrasonic welding to remove an oxidation layer between the contact pads and the conductive bumps. The conductive bumps electrically couple to a conductive coating applied around the periphery of the semiconductor device.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 22, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Jiandi Du, Binbin Zheng, Rui Guo, Chin-Tien Chiu, Zengyu Zhou, Fen Yu
  • Publication number: 20220406724
    Abstract: A semiconductor device has vertical contact fingers formed in a substrate having side portions that are flexible. Contact fingers are formed near one or more edges of the flexible side portions of the substrate. After semiconductor dies are mounted to and electrically coupled to the substrate, the semiconductor device may be encapsulated by placing the device in a mold chase including upper and lower mold plates. The lower mold plate is sized smaller than the substrate so that the flexible side portions of the substrate including the contact fingers fold vertically upward to fit within the mold.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 22, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zhongli Ji, Ning Ye, Chin-Tien Chiu, Fen Yu
  • Publication number: 20220375896
    Abstract: A method and apparatus for substrate component layout and bonding for increased package capacity. According to certain embodiments, a wire-bonding finger strip is disposed between a flip-chip die and a NAND die stack to reduce a keep out zone (KOZ) required for an underfill material dispensed beneath the flip-chip die. To further inhibit the flow of the underfill material and further reduce the KOZ, a solder mask may be placed adjacent to the flip-chip. According to certain embodiments, there may be at least three sides of the flip-chip that may have such an adjacent solder mask placement. The three sides of the flip-chip according to such embodiments may be those non-adjacent to the wire-bonding finger strip.
    Type: Application
    Filed: May 18, 2021
    Publication date: November 24, 2022
    Inventors: Jiandi DU, Zengyu ZHOU, Rui YUAN, Fen YU, Hope CHIU
  • Patent number: 11488883
    Abstract: A semiconductor device package includes a substrate, a heat-generating component positioned on a surface of the substrate, and an encapsulant at least partially covering the heat-generating component and having an outer surface. A first heat-conducting layer is disposed between the encapsulant and the first heat-generating component. One or more pillars are in contact with the first heat-conducting layer and extend to the outer surface of the encapsulant and contact a second heat-conducting layer disposed on the outer surface of the encapsulant.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: November 1, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yazhou Zhang, Jiandi Du, Hope Chiu, Cong Zhang, Fen Yu, Ada Shen, Gary Zheng, Honny Chen
  • Publication number: 20220328374
    Abstract: A semiconductor device package includes a substrate, a heat-generating component positioned on a surface of the substrate, and an encapsulant at least partially covering the heat-generating component and having an outer surface. A first heat-conducting layer is disposed between the encapsulant and the first heat-generating component. One or more pillars are in contact with the first heat-conducting layer and extend to the outer surface of the encapsulant and contact a second heat-conducting layer disposed on the outer surface of the encapsulant.
    Type: Application
    Filed: April 13, 2021
    Publication date: October 13, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Yazhou Zhang, Jiandi Du, Hope Chiu, Cong Zhang, Fen Yu, Ada Shen, Gary Zheng, Honny Chen
  • Patent number: 9704797
    Abstract: A wire bonded structure for a semiconductor device is disclosed. The wire bonded structure comprises a bonding pad; and a continuous length of wire mutually diffused with the bonding pad, the wire electrically coupling the bonding pad with a first electrical contact and a second electrical contact different from the first electrical contact.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: July 11, 2017
    Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.
    Inventors: Zhong Lu, Fen Yu, Chin Tien Chiu, Cheeman Yu, Fuqiang Xiao
  • Publication number: 20140183727
    Abstract: A wire bonded structure for a semiconductor device is disclosed. The wire bonded structure comprises a bonding pad; and a continuous length of wire mutually diffused with the bonding pad, the wire electrically coupling the bonding pad with a first electrical contact and a second electrical contact different from the first electrical contact.
    Type: Application
    Filed: May 18, 2011
    Publication date: July 3, 2014
    Applicants: SANDISK INFORMATION TECHNOLOGY (SHANGHAI) CO., LTD., SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD.
    Inventors: Zhong Lu, Fen Yu, Chin Tien Chiu, Cheeman Yu, Fuqiang Xiao
  • Publication number: 20130052276
    Abstract: Disclosed is a method for making an antimicrobial material from 1D nanometer silver that does not accumulate in a human body. At first, 1D nanometer silver is mixed in hydrophilic solution to produce 1D nanometer silver solution. Then, adhesive is blended in the 1D nanometer silver solution to produce the antimicrobial material. The antimicrobial material may be used in antimicrobial liquid, antimicrobial dressing or antimicrobial composite. Human skin can easily block the 1D nanometer silver. Therefore, the 1D nanometer silver does not enter or accumulate in the human body. Yet, the antimicrobial material exhibits a high bactericidal rate.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Applicant: Chung-Shan Institute of Science and Technology Armaments, Bureau, ministry of National Defence
    Inventors: Yi-Hsiuan Yu, Ming-Hsiung Wei, Lea-Hwung Leu, Kai-Yai Chang, Shen-fey Yeh, Fen-Yu Chung, Chen-Chi Ma
  • Publication number: 20110184272
    Abstract: A portable diagnostic device for cervical precancerous lesions is disclosed. The device includes an inherent fluorescence detection system for cervical cancer, a cervix acetic acid coloring detection and an image collection system. The inherent fluorescence detection system for cervical cancer has a light source and a switch, which consists of a excitation light source that generates fluorescence and a cold light source that generates white light, both the excitation light source and the cold light source are installed in the bowl-shaped reflector with specific focal length. The cervix acetic acid coloring detection system has an acetic acid pool, a spraying tube that connects with the acetic acid pool, a spraying tube moving device, and a spraying switch. The image collection system has a weak light CCD, which is installed in the center of the bowl-shaped reflector.
    Type: Application
    Filed: January 12, 2009
    Publication date: July 28, 2011
    Inventors: Kun Zeng, Zhen Fen Yu
  • Patent number: 7831955
    Abstract: An architecture for development and execution of a system for implementing business logic includes an engine providing management of the system and execution of the business logic. A single service-side interface connects the engine to service side plug-in modules, and a single resource side interface connects the engine with resource-side plug-in modules. The server-side and resource-side plug-in modules connect to users and resources, respectively. The single interfaces conform the plug-in module interfaces to one interface to communicate with the engine. The single interfaces employ a single command definition. Development code defining the business logic is written by a user and executed by the engine.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: November 9, 2010
    Assignee: Asift Technologies, LLC
    Inventors: Tomoyoshi Tamura, Esther Yu-Fen Yu
  • Publication number: 20080047108
    Abstract: A handle structure includes a gripping portion and a hinge portion. The gripping portion includes a handle and two levers. Each lever has a first hole, a second hole and a groove adjacent to the second hole. The handle is inserted into those second holes by pressing the handle toward the grooves. The hinge portion includes two flexible clamps. Each flexible clamp includes two protrusions against each other. The end with the first hole of the gripping portion presses the two protrusions to move apart from each other. Then, the protrusions are inserted in the first holes, and the gripping portion can swing around the hinge portion.
    Type: Application
    Filed: July 6, 2007
    Publication date: February 28, 2008
    Applicant: BENQ CORPORATION
    Inventor: Sun-Fen Yu