Abstract: A semiconductor package includes an insulation layer provided between a molding compound and an electromagnetic interface (EMI) layer. The insulation layer covers an exposed portion of a bond wire that extends beyond a top surface of the molding compound due to a Z-height reduction of the molding compound. The insulation layer prevents a short from occurring between the bond wire and the EMI layer.

Abstract: A thickness of a signal trace on a printed circuit board (PCB) or a substrate is increased by intentionally forming a solder bridge on a surface of the signal trace during a reflow process in which a flip chip die or other computing component is mounted to the PCB or the substrate. Specifically, adjacent interconnects of the flip chip die are coupled to the same signal trace on the PCB or the substrate. During the reflow process, solder associated with each interconnect flows into a space or area defined by the adjacent interconnects and forms a solder bridge within the space, thereby increasing a thickness of the signal trace.

Abstract: A wire bonder has a rotatable capillary for forming a stitch bond on a bonding surface of a connection point. When the stitch bond is formed, a bond head of the wire bonder causes the capillary to rotate in a XY plane. Rotation of the capillary causes at least a portion of the stitch bond to contact one or more side walls of the connection point. As a result, an entire surface area of the stitch bond contacts one or more surfaces of the connection point.

Abstract: A semiconductor device package includes a semiconductor die including bond pads and an underfill inlet side, a substrate including a first metal layer and lower metal layers underneath the first metal layer, a plurality of metal contacts and trace segment lines disposed in the first metal layer, and a plurality of solder bump rows. Each of the solder bump rows is oriented substantially parallel to the inlet side of the semiconductor die and electrically connects bond pads of the semiconductor die with corresponding metal contacts in the first metal layer of the substrate. Each of the trace segment lines is oriented substantially parallel to the inlet side of the semiconductor die, is electrically coupled to a respective solder bump row of the plurality of solder bump rows, and includes trace segments disposed in the first metal layer and trace segments disposed in one or more of the lower metal layers.

Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.

Abstract: A semiconductor controller includes a controller semiconductor die having an integrated thermal interface material layer, or TIM formed on top of the die. In embodiments, the controller semiconductor die may be mounted on a substrate, for example in a flip-chip configuration. Thereafter, the TIM may be positioned on an upper surface of the controller semiconductor die and the TIM and controller semiconductor die may be positioned within a mold chase for encapsulation in mold compound. After encapsulation, the TIM may be exposed in an upper surface of the encapsulated controller semiconductor die.

Abstract: A semiconductor device includes a semiconductor controller die and a stack of one or more semiconductor memory dies. In one example, the controller die may have an integrated heat sink window plate, or HSWP, formed on top of the die. In other examples, an uppermost memory die in the stack of memory dies may include an integrated HSWP. The HSWP may be formed on the controller die and/or the memory die at the wafer level.

Abstract: A semiconductor package includes a multifunctional interface material (MIM) structure provided on a stack of memory dies. The MIM structure includes an adhesive layer disposed directly over a top surface of the top memory die of the stack of memory dies. The MIM structure also includes a polymer layer disposed directly over the adhesive layer. The adhesive layer of the MIM structure receives and secures a portion of the wires of the semiconductor package that contact the top memory die to minimize undesirable movement and disconnection of the wires from the top memory die. The polymer layer of the MIM structure compresses the adhesive layer to aid in securing the wires within the adhesive layer. The polymer layer also protects the adhesive layer within the semiconductor package during operation.

Abstract: An apparatus includes a tape having a tape thickness extending from a first surface to a second surface and a plurality of cavities formed in the first surface. Each cavity has dimensions along the first surface that are less than dimensions of a corresponding package. Each cavity has a cavity depth that is less than the tape thickness such that a base portion of the tape has a base thickness that is less than the tape thickness.

Abstract: A wire bonder has a rotatable capillary for forming a stitch bond on a bonding surface of a connection point. When the stitch bond is formed, a bond head of the wire bonder causes the capillary to rotate in a XY plane. Rotation of the capillary causes at least a portion of the stitch bond to contact one or more side walls of the connection point. As a result, an entire surface area of the stitch bond contacts one or more surfaces of the connection point.

Abstract: A semiconductor package includes an insulation layer provided between a molding compound and an electromagnetic interface (EMI) layer. The insulation layer covers an exposed portion of a bond wire that extends beyond a top surface of the molding compound due to a Z-height reduction of the molding compound. The insulation layer prevents a short from occurring between the bond wire and the EMI layer.

Abstract: A memory device includes a substrate, a controller die attached to the substrate, and a memory die stack. The memory die stack includes a first silicon die having a first contact pad surface and a bottom surface attached to the substrate. The memory die stack includes a second silicon die stacked on the first silicon die, the second silicon die including a second contact pad surface. An overhang portion of the second silicon die extends beyond the first silicon die. The memory die stack includes a printed support structure attached to the substrate, the printed support structure supporting the overhang portion of the second silicon die, and one or more bond wires that electrically connect the first and second contact pad surfaces to the substrate, thereby electrically connecting the first and second silicon dies to the controller die by way of the substrate.

Abstract: A method of forming a semiconductor device includes forming vertical contact fingers in a substrate having side portions that are flexible. Contact fingers are formed near one or more edges of the flexible side portions of the substrate. After semiconductor dies are mounted to and electrically coupled to the substrate, the semiconductor device may be encapsulated by placing the device in a mold chase including upper and lower mold plates. The lower mold plate is sized smaller than the substrate so that the flexible side portions of the substrate including the contact fingers fold vertically upward to fit within the mold.

Abstract: A thickness of a signal trace on a printed circuit board (PCB) or a substrate is increased by intentionally forming a solder bridge on a surface of the signal trace during a reflow process in which a flip chip die or other computing component is mounted to the PCB or the substrate. Specifically, adjacent interconnects of the flip chip die are coupled to the same signal trace on the PCB or the substrate. During the reflow process, solder associated with each interconnect flows into a space or area defined by the adjacent interconnects and forms a solder bridge within the space, thereby increasing a thickness of the signal trace.

Abstract: A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The first stack of memory dies includes a first substack of staggered memory dies offset with respect to each other in a first direction and a second substack of staggered memory dies offset with respect to each other in the first direction and positioned above the first substack. The second stack of memory dies includes a third substack of staggered memory dies offset with respect to each other in a second direction and a fourth substack of staggered memory dies offset with respect to each other in the second direction and positioned above the third substack. The top memory die of the first substack and a memory die positioned below the top memory die of the third substack are at least partially coplanar.

Abstract: A method and apparatus for substrate component layout and bonding for increased package capacity. According to certain embodiments, a wire-bonding finger strip is disposed between a flip-chip die and a NAND die stack to reduce a keep out zone (KOZ) required for an underfill material dispensed beneath the flip-chip die. To further inhibit the flow of the underfill material and further reduce the KOZ, a solder mask may be placed adjacent to the flip-chip. According to certain embodiments, there may be at least three sides of the flip-chip that may have such an adjacent solder mask placement. The three sides of the flip-chip according to such embodiments may be those non-adjacent to the wire-bonding finger strip.

Abstract: A semiconductor device has shielding to prevent transmission and/or reception of EMI and/or RFI radiation. The semiconductor device comprises a substrate including grounded contact pads around a periphery of the substrate, exposed at one or more edges of the substrate. A bump made of gold or other non-oxidizing conductive material may be formed on the contact pads, for example using ultrasonic welding to remove an oxidation layer between the contact pads and the conductive bumps. The conductive bumps electrically couple to a conductive coating applied around the periphery of the semiconductor device.

Abstract: A semiconductor device package includes a semiconductor die including bond pads and an underfill inlet side, a substrate including a first metal layer and lower metal layers underneath the first metal layer, a plurality of metal contacts and trace segment lines disposed in the first metal layer, and a plurality of solder bump rows. Each of the solder bump rows is oriented substantially parallel to the inlet side of the semiconductor die and electrically connects bond pads of the semiconductor die with corresponding metal contacts in the first metal layer of the substrate. Each of the trace segment lines is oriented substantially parallel to the inlet side of the semiconductor die, is electrically coupled to a respective solder bump row of the plurality of solder bump rows, and includes trace segments disposed in the first metal layer and trace segments disposed in one or more of the lower metal layers.

Abstract: A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The first stack of memory dies includes a first substack of staggered memory dies offset with respect to each other in a first direction and a second substack of staggered memory dies offset with respect to each other in the first direction and positioned above the first substack. The second stack of memory dies includes a third substack of staggered memory dies offset with respect to each other in a second direction and a fourth substack of staggered memory dies offset with respect to each other in the second direction and positioned above the third substack. The top memory die of the first substack and a memory die positioned below the top memory die of the third substack are at least partially coplanar.

Abstract: A semiconductor device has vertical contact fingers formed in a substrate having side portions that are flexible. Contact fingers are formed near one or more edges of the flexible side portions of the substrate. After semiconductor dies are mounted to and electrically coupled to the substrate, the semiconductor device may be encapsulated by placing the device in a mold chase including upper and lower mold plates. The lower mold plate is sized smaller than the substrate so that the flexible side portions of the substrate including the contact fingers fold vertically upward to fit within the mold.