Patents by Inventor Feng-An Yang

Feng-An Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384454
    Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Yu-Chia Liang, Shih-Hao Lin, Kuei-Lun Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20220383997
    Abstract: A data processing method, a data processing apparatus, and a health management apparatus. The data processing method includes: performing data processing on device-related data from a device associated with a health management apparatus. The data processing apparatus and the health management apparatus can improve the uniformity of memories provided to be associated with the health management apparatus.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Zhou Wang, Zigang Liu, Yuan Gao, Tongbo Wang, Guilong Yang, Feng Qi, Yang Han
  • Publication number: 20220382378
    Abstract: A method for identifying an object, an optical sensing apparatus and a system are provided. A controller of the system drives multiple light sources of the optical sensing apparatus to emit the multiple light beams with different beam angles, controls a light sensor to sense the lights reflected by the object, and performs the method for identifying the object. In the method, the light sensor is used to sense a first light emitted by a first light source with a first beam angle reflected by the object, and sense an intensity of the reflected first light. The light sensor is also used to sense a second light emitted by a second light source with a second beam angle reflected by the object and sense another intensity of the reflected second light. Therefore, the object can be identified by integrating information of the intensities obtained by the light sensor.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Inventors: TIEN-CHUNG YANG, CHIA-KAI CHEN, EN-FENG HSU, CHEN-LUNG LIU
  • Publication number: 20220384654
    Abstract: Methods and devices formed thereof that include a fin structure extending from a substrate and a gate structure is formed over the fin structure. An epitaxial feature is formed over the fin structure adjacent the gate structure. The epitaxial feature can include a hollow region (or dielectric filled hollow region) in the epitaxial source/drain region. A selective etching process is performed to remove at least a portion of an epitaxial region having a second dopant type to form the hollow area between the first epitaxial portion and the third epitaxial portion.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Inventors: Feng-Ching CHU, Wei-Yang LEE, Feng-Cheng YANG, Yen-Ming CHEN
  • Publication number: 20220384442
    Abstract: A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define a void therebetween. The second spacer seals the void between the first spacer and the epitaxy structure. The dielectric residue is in the void and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has a silicon-to-nitrogen atomic ratio higher than a silicon-to-nitrogen atomic ratio of the lower portion of the dielectric residue.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Yu LAI, Kai-Hsuan LEE, Wei-Yang LEE, Feng-Cheng YANG, Yen-Ming CHEN
  • Publication number: 20220382169
    Abstract: A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.
    Type: Application
    Filed: June 21, 2021
    Publication date: December 1, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Min Cheng Yang, Wei Cyuan Lo, Yung-Feng Cheng
  • Patent number: 11514621
    Abstract: The disclosure provides a low-dose image reconstruction method and system based on prior anatomical structure difference.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: November 29, 2022
    Assignee: SHENZHEN INSTITUTES OF ADVANCED TECHNOLOGY
    Inventors: Zhan Li Hu, Dong Liang, Hai Rong Zheng, Xin Liu, Yong Feng Yang, Zhen Xing Huang
  • Patent number: 11514445
    Abstract: Examples in this application disclose information sharing computer-implemented methods, media, and systems. One example computer-implemented method includes obtaining, from an external server at a trusted execution environment (TEE), a trigger instruction, in response to obtaining the trigger instruction, combining, at the TEE, first anti-money laundering (AML) risk information provided by a first institution and second AML risk information provided by a second institution to obtain third AML risk information, where the first AML risk information and the second AML risk information correspond to a user identifier, and sending, from the TEE to the first institution, the third AML risk information.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: November 29, 2022
    Assignee: Alipay (Hangzhou) Information Technology Co., Ltd.
    Inventors: Yuan Chen, Renhui Yang, Xinmin Wang, Wenyu Yang, Feng Qian, Qianting Guo, Shubo Li
  • Patent number: 11516934
    Abstract: A wearable device is provided, including a shell, a body installed in the shell to implement a function of the wearable device, and a detachable part. The detachable part is detachably installed on the shell. An air hole is provided on the shell, a first end of the air hole is located on a surface of the shell that faces the body, and a second end of the air hole is located on a surface of the shell that faces away from the body. The detachable part and the shell jointly form a dirt collection groove and at least one air channel, the air hole communicates with the at least one air channel through the dirt collection groove, and an end of the air channel that faces away from the dirt collection groove communicates with an external environment of the shell.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: November 29, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jun Yang, Zhihong Tang, Feng Tian, Jiawei Lv
  • Patent number: 11515211
    Abstract: A method includes etching two source/drain regions over a substrate to form two source/drain trenches; epitaxially growing two source/drain features in the two source/drain trenches respectively; performing a cut process to the two source/drain features; and after the cut process, depositing a contact etch stop layer (CESL) over the two source/drain features.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Chia-Pin Lin
  • Patent number: 11516579
    Abstract: An embodiment for cancelling echo in online conference systems is provided. According to some embodiments of the present disclosure, the computer-implemented method comprises, in response to an update of devices of participants in an online conference, dividing, by one or more processors, the devices in an online conference into a plurality of groups, wherein the devices located in a same physical location are divided into a same group. The method also comprises, in response to an update of the devices in an online conference, selecting at least one speaker of the devices in each of the plurality of groups as a representative speaker for each of the plurality of groups. The method further comprises forwarding audio data received from microphones of the devices in one of the plurality of groups to the respective representative speaker of other groups of the plurality of groups.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 29, 2022
    Assignee: International Business Machines Corporation
    Inventors: Kai Feng, Yun Juan Yang, Xiao Zhen Zhu, Ming Dong, Yang Cao, Jing Hua Jiang, Yan Hui Wang, Jia Lei Rui, Qi Li
  • Publication number: 20220372554
    Abstract: A direct chemical lysis composition includes an assay compatible buffer composition and an assay compatible surfactant. When combined with a specimen storage composition, such compositions prevent undesired modifications to nucleic acid and proteins lysed from cells in the biological sample. Assays of samples from such compositions do not require expensive and time-consuming steps such as centrifugation and prolonged high temperature processing. The direct chemical lysis composition of the present invention permits direct nucleic acid extraction from the cells in the biological sample without the need to decant off the transport media or otherwise exchange the transport media with assay compatible buffers. There is no need to combine the sample with proteinase K or another enzyme to extract nucleic acids from the cells. A method for lysing cells to obtain target nucleic acid for assay and a kit for combining the direct chemical lysis composition with a sample are also contemplated.
    Type: Application
    Filed: August 8, 2022
    Publication date: November 24, 2022
    Inventors: Feng Yang, Sha-Sha Wang, Laurence Michael Vaughan, Michael Porter, Elaine Rose
  • Publication number: 20220377816
    Abstract: Systems and methods of setting up an E1 interface for a gNB are described, A transmitting entity of the gNB-CU-CP and gNB-CU-UP initiates the first TNL association between the gNB-CU-CP and gNB-CU-UP, and is also limited to initiating the E1 Setup procedure. The transmitting entity sends an E1 SETUP REQUEST message to set up the E1 interface. Afterwards, a message is received from the receiving entity. The transmitting entity determines that the setup of the E1 interface is successful if the message contains IEs of an E1 SETUP RESPONSE message. The types of IEs include a message type IE and a name of the transmitting entity.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 24, 2022
    Inventors: Feng Yang, Alexander Sirotkin, Jaemin Han, Xu Zhang
  • Patent number: 11508736
    Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11508048
    Abstract: The present disclosure discloses a method and a system for generating a composite PET-CT image based on a non-attenuation-corrected PET image. The method includes: constructing a first generative adversarial network and a second generative adversarial network; obtaining a mapping relationship between a non-attenuation-corrected PET image and an attenuation-corrected PET image by training the first generative adversarial network; obtaining a mapping relationship between the attenuation-corrected PET image and a CT image by training the second generative adversarial network; and generating the composite PET-CT image by utilizing the obtained mapping relationships. According to the present disclosure, a high-quality PET-CT image can be directly composited from a non-attenuation-corrected PET image, and medical costs can be reduced for patients, and radiation doses applied to the patients in examination processes can be minimized.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: November 22, 2022
    Assignee: SHENZHEN INSTITUTES OF ADVANCED TECHNOLOGY
    Inventors: Zhan Li Hu, Dong Liang, Yong Chang Li, Hai Rong Zheng, Yong Feng Yang, Xin Liu
  • Publication number: 20220363603
    Abstract: A cerium-zirconium-aluminum-based composite material, a cGPF catalyst and a preparation method thereof are provided. The cerium-zirconium-aluminum-based composite material adopts a stepwise precipitation method, firstly preparing an aluminum-based pre-treated material, then coprecipitating the aluminum-based pre-treated material with zirconium and cerium sol, and finally roasting at high temperature to obtain the cerium-zirconium-aluminum-based composite material. The cerium-zirconium-aluminum-based composite material has better compactness and higher density, and when it is used in cGPF catalyst, it occupies a smaller volume of pores on the catalyst carrier, such that cGPF catalyst has lower back pressure and better ash accumulation resistance, which is beneficial to large-scale application of cGPF catalyst.
    Type: Application
    Filed: June 17, 2020
    Publication date: November 17, 2022
    Inventors: Dacheng LI, Jinfeng WANG, Li LAN, Hui YE, Lan YANG, Feng ZHANG, Yi YANG, Yongxiang CHENG, Tiantian LUO, Yinhua DONG, Yun WANG, Yun LI, Qizhang CHEN
  • Publication number: 20220367277
    Abstract: A device includes a substrate, an isolation structure over the substrate, and two fins extending from the substrate and above the isolation structure. Two source/drain structures are over the two fins respectively and being side by side along a first direction generally perpendicular to a lengthwise direction of the two fins from a top view . Each of the two source/drain structures has a near-vertical side, the two near-vertical sides facing each other along the first direction. A contact etch stop layer (CESL) is disposed on at least a lower portion of the near-vertical side of each of the two source/drain structures. And two contacts are disposed over the two source/drain structures, respectively, and over the CESL.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Chia-Pin Lin
  • Publication number: 20220367722
    Abstract: An IGZO thin-film transistor and a method for manufacturing same. The method comprises: acquiring a substrate; forming an IGZO layer on the substrate by means of a solution process; doping V impurities on a surface of the IGZO layer by means of a spin doping process; forming a source electrode at one side of the IGZO layer, and forming a drain electrode at the other side thereof; forming a gate dielectric layer on the doped IGZO layer; and forming a gate electrode on the gate dielectric layer.
    Type: Application
    Filed: August 26, 2020
    Publication date: November 17, 2022
    Inventors: Wangran WU, Guangan YANG, Feng LIN, Guipeng SUN, Yaohui WANG, Weifeng SUN, Longxing SHI
  • Publication number: 20220367720
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 17, 2022
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Chia-Pin Lin
  • Patent number: D971125
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: November 29, 2022
    Inventors: Feng Wang, Wen Shao, Yan Cong, Jinlin Wang, Jixuan Yang, Tian Yang