Patents by Inventor FENG-CHANG CHIEN

FENG-CHANG CHIEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230413426
    Abstract: A circuit board assembly in a camera module for blocking unwanted light when images are captured includes a circuit board, a sensor, and an optical blocking body connecting the circuit board and the sensor. The circuit board includes a base board and a photomask. The photomask is arranged on a surface of the base board, the base board includes conductive circuit layers and dielectric layers, the conductive circuit layers and the dielectric layers are alternately arranged, the sensor being electronically connected to the conductive layers. The optical blocking body, the photomask, and the dielectric layers block ambient light entering the camera module other than through the lens assembly of the camera module.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 21, 2023
    Inventors: YING-LIN CHEN, CHIA-WENG HSU, PING-LIANG ENG, FENG-CHANG CHIEN
  • Patent number: 6930323
    Abstract: A test keys structure comprises a plurality of test keys in scribe lines of a control monitor wafer. Between 50 and 400 test keys are formed on the control monitor wafer, and each of the plurality of test keys has an area of at least 1E6?m2.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: August 16, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Tsong Chen, Ming-Shuo Yen, Woan Tyng Hwang, Yu-Chang Chen, Tien-Tzu Wen, Shion-Feng Chang Chien
  • Patent number: 6623995
    Abstract: A method of early and effective detection of defects in a metal patterning process is described. A test keys structure is provided comprising a plurality of test keys in scribe lines of a control monitor wafer wherein more than 300 test keys are formed on a control monitor wafer and wherein each of the plurality of test keys has an area of at least 106 &mgr;m2. A metal layer is deposited on the control monitor wafer. A dielectric layer is deposited overlying the metal layer. Thereafter, the control monitor wafer is tested using the plurality of test keys.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: September 23, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsien-Tsong Chen, Ming-Shuo Yen, Woan Tyng Hwang, Yu-Chang Chen, Tien-Tzu Wen, Shion-Feng Chang Chien