Patents by Inventor Feng Cheng
Feng Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12382692Abstract: A method includes forming a structure having a dummy gate stack over a fin protruding from a substrate. The fin includes an ML of alternating semiconductor layers and sacrificial layers. The method further includes forming a recess in an S/D region of the ML, forming a recess of the ML, and forming inner spacers on sidewalls of the sacrificial layers. Each inner spacer includes a first layer embedded in the sacrificial layer and a second layer over the first layer. The method further includes forming an S/D feature in the recess, such that the second layer of the inner spacers is embedded in the S/D feature. The method further includes removing the dummy gate stack to form a gate trench, removing the sacrificial layers from the ML, thereby forming openings interleaved between the semiconductor layers, and subsequently forming a high-k metal gate stack in the gate trench and the openings.Type: GrantFiled: April 10, 2023Date of Patent: August 5, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: I-Hsieh Wong, Wei-Yang Lee, Yen-Ming Chen, Feng-Cheng Yang
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Patent number: 12376351Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.Type: GrantFiled: February 12, 2024Date of Patent: July 29, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sai-Hooi Yeong, Feng-Cheng Yang, Yih-Ann Lin, Yen-Ming Chen
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Patent number: 12362276Abstract: A semiconductor device including an integrated circuit, a dielectric layer, a plurality of connecting terminals and at least one dummy conductor is provided. The integrated circuit has a plurality of connecting pads, and the dielectric layer is disposed thereon and partially exposes the plurality of the connecting pads by a plurality of openings defined therein. The plurality of the connecting terminals is disposed on the plurality of the connecting pads exposed by the plurality of the openings. The at least one dummy conductor is disposed on the dielectric layer and electrically isolated from the integrated circuit. A substantial topology variation is between the plurality of the connecting terminals and the at least one dummy conductor. A semiconductor package having the semiconductor device is also provided.Type: GrantFiled: June 9, 2022Date of Patent: July 15, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Cheng Hsu, Shin-Puu Jeng
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Patent number: 12363911Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a stacked structure disposed on the substrate. The stacked structure includes multiple alternately stacked insulating layers and gate members. A core structure is disposed in the stacked structure. The core structure includes a memory layer, a channel member, a contact member, and a liner member. The channel member is disposed on the memory layer. The contact member is disposed on the channel member. The liner member surrounds a portion of the core structure. The present disclosure also provides a method for fabricating the semiconductor structure.Type: GrantFiled: July 18, 2023Date of Patent: July 15, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Wei Jiang, Sheng-Chih Lai, Feng-Cheng Yang, Chung-Te Lin
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Patent number: 12356707Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.Type: GrantFiled: July 31, 2023Date of Patent: July 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Te Lin, Wei-Yuan Lu, Feng-Cheng Yang
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Publication number: 20250203874Abstract: A device includes a dielectric pattern, a first dielectric layer, a stack and a conductive pillar. The first dielectric layer is disposed on the dielectric pattern, wherein a material of the dielectric pattern is different from a material of the first dielectric layer. The stack is disposed on the first dielectric layer. The conductive pillar extends along the stack, wherein the conductive pillar penetrates through the first dielectric layer and disposed on the dielectric pattern.Type: ApplicationFiled: February 25, 2025Publication date: June 19, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Han-Jong Chia, Feng-Cheng Yang
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Patent number: 12332390Abstract: The online detection system for type identification and activity measurement of radiations in gas or liquid is provided, which can capture the light signals generated by different radiations in real time, and convert the light signals into the electrical signals, so as to realize the online type identification and activity measurement of the radiations based on the waveforms and the time information of the electrical signals of the different radiations. In addition, based on the characteristic that different radiations have different penetration capabilities, the inner-outer two-layer activity measurement structure is designed, which can discriminate the radiations with the same waveform. Therefore, the present disclosure simplifies the radiation activity measurement process, thereby greatly improving the efficiency of the radiation activity measurement.Type: GrantFiled: March 27, 2023Date of Patent: June 17, 2025Inventors: Chunhui Dong, Ming Wang, Qingxian Zhang, Gang Li, Qichang Huang, Lingfeng Wei, Weinan Li, Jingxin Zuo, Weixin Peng, Kaiyong Liao, Yi Gu, Feng Cheng, Fei Li, Muhao Zhang
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Publication number: 20250194227Abstract: A semiconductor device and methods of forming the semiconductor device are described herein and are directed towards forming a source/drain contact plug for adjacent finFETs. The source/drain regions of the adjacent finFETs are embedded in an interlayer dielectric and are separated by an isolation region of a cut-metal gate (CMG) structure isolating gate electrodes of the adjacent finFETs The methods include recessing the isolation region, forming a contact plug opening through the interlayer dielectric to expose portions of a contact etch stop layer disposed over the source/drain regions through the contact plug opening, the contact etch stop layer being a different material from the material of the isolation region. Once exposed, the portions of the CESL are removed and a conductive material is formed in the contact plug opening and in contact with the source/drain regions of the adjacent finFETs and in contact with the isolation region.Type: ApplicationFiled: February 24, 2025Publication date: June 12, 2025Inventors: Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 12322742Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.Type: GrantFiled: November 24, 2023Date of Patent: June 3, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
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Patent number: 12324201Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.Type: GrantFiled: February 5, 2024Date of Patent: June 3, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Feng-Ching Chu, Wei-Yang Lee, Yen-Ming Chen, Feng-Cheng Yang
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Publication number: 20250176183Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.Type: ApplicationFiled: January 28, 2025Publication date: May 29, 2025Inventors: Feng-Ching Chu, Feng-Cheng Yang, Katherine H. Chiang, Chung-Te Lin, Chieh-Fang Chen
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Patent number: 12315762Abstract: A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.Type: GrantFiled: November 10, 2021Date of Patent: May 27, 2025Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yong-Jie Wu, Yen-Chung Ho, Hui-Hsien Wei, Chia-Jung Yu, Pin-Cheng Hsu, Feng-Cheng Yang, Chung-Te Lin
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Patent number: 12317541Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a semiconductor channel layer, a gate dielectric layer, a source terminal and a drain terminal. The semiconductor channel layer is disposed over and above the gate. The gate dielectric layer is disposed between the gate and the semiconductor channel layer. The source terminal and the drain terminal are disposed on the semiconductor channel layer. A contact plug is disposed on at least one of the source terminal and the drain terminal. A dielectric pattern surrounds the contact plug and covers the source terminal and the drain terminal. A gas barrier layer is disposed on the dielectric pattern and surrounding the contact plug.Type: GrantFiled: January 25, 2022Date of Patent: May 27, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Wei Jiang, Sheng-Chih Lai, Feng-Cheng Yang, Chung-Te Lin
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Publication number: 20250167158Abstract: A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip over the first surface. The chip package structure includes a second chip over the second surface. The chip package structure includes a conductive pillar over the second surface and adjacent to the second chip. The chip package structure includes a molding layer over the second surface and surrounding the second chip. The chip package structure includes a second redistribution structure over the second chip. The chip package structure includes a buffer layer between the second redistribution structure and the second chip. The chip package structure includes a third chip over the second redistribution structure.Type: ApplicationFiled: January 17, 2025Publication date: May 22, 2025Inventors: Shin-Puu JENG, Shuo-Mao CHEN, Feng-Cheng HSU
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Publication number: 20250169159Abstract: A semiconductor device includes a substrate, an isolation feature disposed on the substrate, first and second fins protruding from the substrate and upwardly through the isolation feature, and a gate stack engaging each of the fins. The semiconductor device also includes a first epitaxial layer having a first portion over top and sidewall surfaces of S/D regions of the first fin and a second portion over top and sidewall surfaces of S/D regions of the second fin, a second epitaxial layer having a first portion over top and sidewall surfaces of the first portion of the first epitaxial layer and a second portion over top and sidewall surfaces of the second portion of the first epitaxial layer. The first and second portions of the second epitaxial layer are spaced apart. Each of the first and second portions of the second epitaxial layer is in physical contact with the isolation feature.Type: ApplicationFiled: January 17, 2025Publication date: May 22, 2025Inventors: Cheng-Yu Yang, Chia-Ta Yu, Kai-Hsuan Lee, Sai-Hooi Yeong, Feng-Cheng Yang
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Publication number: 20250169170Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.Type: ApplicationFiled: January 17, 2025Publication date: May 22, 2025Inventors: Yen-Ting Chen, Bo-Yu Lai, Chien-Wei Lee, Hsueh-Chang Sung, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
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Publication number: 20250159888Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.Type: ApplicationFiled: January 16, 2025Publication date: May 15, 2025Inventors: Sheng-Chen Wang, Feng-Cheng Yang, Meng-Han Lin, Han-Jong Chia
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Publication number: 20250159895Abstract: A device includes a first conductive feature, an etch stop layer, a plurality of stacks, a first conductive pillar and dielectric patterns. The etch stop layer is disposed on the first conductive feature. The stacks are disposed on the etch stop layer. The first conductive pillar extends between opposite surfaces of the stacks. The dielectric patterns are disposed at opposite sidewalls of a portion of the first conductive pillar in the etch stop layer.Type: ApplicationFiled: January 15, 2025Publication date: May 15, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Feng-Cheng Yang
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Publication number: 20250146834Abstract: The present disclosure provides a method and a system for adaptively dividing a graph network comprising a plurality of nodes, each of the plurality of nodes being connected to at least one other node of the plurality of nodes, the method comprising: for each pair of subnetworks from a plurality of subnetworks within the graph network, calculating an association score based on a first accuracy metric in predicting a first latent attribute of at least one first node of a first subnetwork of the each pair of subnetworks using parameters optimized for accurately predicting a second latent attribute of at least one second node of a second subnetwork of the each pair of subnetworks; and forming one of a plurality of new subnetworks within the graph network from each pair of a pair set of subnetworks from the plurality of subnetworks based on a result of determining a sum of the association scores of the pair set of subnetworks is higher than that of another pair set of subnetworks from the plurality of subnetworksType: ApplicationFiled: March 28, 2023Publication date: May 8, 2025Inventors: Johan Zhi Kang KOK, Suriyanarayanan VENKATESAN, Sien Yi TAN, Feng CHENG, Bingsheng HE
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Patent number: D1080868Type: GrantFiled: February 18, 2022Date of Patent: June 24, 2025Assignee: CLEARMIND BIOMEDICAL, INC.Inventors: Sheng-Chi Lin, Feng-Cheng Chang, Yi-Chen Wang, Yu-Jen Lin