Abstract: An electronic includes an electronic element, an encapsulation layer surrounding the electronic element, a first circuit structure, a second circuit structure and a connecting structure. The encapsulation layer has a top surface, a bottom surface and an opening, wherein a sidewall of the opening connects the top surface and the bottom surface. The first circuit structure is disposed at the top surface of the encapsulation layer. The second circuit structure is disposed at the bottom surface of the encapsulation layer. The connecting structure is disposed in the opening, wherein the electronic element is electrically connected to the second circuit structure through the first circuit structure and the connecting structure. The connecting structure includes a first sub layer and a second sub layer, the first sub layer is located between the encapsulation layer and the second sub layer, and the first sub layer covers the sidewall of the opening.

Abstract: An image-sensor device is provided. The image-sensor device includes a semiconductor substrate and a radiation-sensing region in the semiconductor substrate. The image-sensor device also includes a doped isolation region in the semiconductor substrate and a dielectric film extending into the doped isolation region from a surface of the semiconductor substrate. A portion of the doped isolation region is between the dielectric film and the radiation-sensing region.

Abstract: The present disclosure provides an electronic device including a first sensing circuit, a second sensing circuit and a power line. The first sensing circuit includes a first sensing unit and a first transistor, and a first end of the first sensing unit is coupled to a control end of the first transistor. The second sensing circuit includes a second sensing unit and a second transistor, and a first end of the second sensing unit is coupled to a control end of the second transistor. A first end of the first transistor and a first end of the second transistor are coupled to the power line.

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

Abstract: Methods, apparatus, and processor-readable storage media for automatically determining work environment-related ergonomic data are provided herein. An example computer-implemented method includes obtaining ergonomic-related data pertaining to one or more of an individual within a work environment and the work environment; determining one or more ergonomic parameter values by processing at least a portion of the obtained ergonomic-related data using one or more models; generating and outputting, to the individual via one or more automated systems, at least one notification based at least in part on the one or more ergonomic parameter values; and performing one or more automated actions based at least in part on one or more of the one or more ergonomic values and the at least one notification.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and a plurality of reset signal lines. The base substrate includes a display region which includes sub-pixels arranged in array, each sub-pixels includes a pixel driving circuit and a light-emitting element. The plurality of reset signal lines extends in a first direction and include a plurality of first reset signal lines for providing a first reset signal and a plurality of second reset signal lines for providing a second reset signal, and one of the plurality of first reset signal lines and one of the plurality of second reset signal lines are respectively connected to pixel driving circuits of a plurality of sub-pixels located in a same row. A layer where the plurality of first reset signal lines are located is different from layers where the plurality of second reset signal lines are located.

Abstract: An optical film, display module, and display screen, wherein the optical film comprises a main body, multiple microstructures, and an opaque layer. The microstructures are positioned on one side of the main body, and these microstructures are protruding arcuate structures. The opaque layer is affixed to the main body and is set opposite the microstructures on the other side of the main body, the opaque layer includes multiple apertures. Wherein, the center point of the apertures overlaps with the center point of the microstructures on a projection plane. Wherein, the equivalent diameter of the apertures divided by the equivalent diameter of the microstructures is less than or equal to 0.3, the equivalent diameter of the microstructures divided by the thickness of the main body is less than or equal to 1.3, and greater than or equal to 0.7. Wherein, the opaque layer is oriented towards the light source.

Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.

Abstract: The disclosure discloses a swirler-type gas-liquid two-phase flow metering device, mainly including a swirler, a capacitance probe module, a hot-wire probe module, a hub and a data acquisition computer. A flow measurement method using the gas-liquid two-phase flow metering device includes: adjusting, by the swirler, flow patterns of an incoming gas-liquid two-phase flow into a uniform annular flow, measuring gas and liquid phase distribution by the capacitance probe module, and measuring gas and liquid phase flow velocity distribution by the hot-wire probe, and volumetric flow rates of gas, thereby obtaining liquid phases according to flow areas and average flow velocities of the gas and liquid phases. Compared with the existing multiphase flowmeter, the gas-liquid two-phase flow metering device of the disclosure has the advantages of small size, compact structure, small resistance loss, wide measurement range, high measurement accuracy, etc.

Abstract: A refrigerant distributor (4) includes: a box body (42); a refrigerant inlet (41) arranged on an upper surface (421) of the box body (42); liquid exit openings (46) evenly arranged on a lower surface (422) of the box body (42); and end plates arranged at both ends of the box body (42) in a length direction and enclosing the box body (42) from the two ends; wherein, in a height direction from the lower surface (422) of the box body (42) to the upper surface (421) and within a predetermined height range starting from the lower surface (422), a width of the box body (42) increases gradually; and a pre-distributor (3) is arranged inside the box body (42).

Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.

Abstract: In one embodiment, a method by an arbiter associated with hardware resources of a computing system includes associating with N indexed requesters requesting accesses to the hardware resources, where each of the N indexed requesters is associated with a credit counter and a weight, repeatedly granting a right to access the hardware resources to each requester that satisfies conditions in an indexing order among the N indexed requesters until none of the N indexed requesters satisfies the conditions and replenishing, upon a determination that none of the N indexed requesters satisfies the conditions, a credit counter associated with each of the N indexed requesters.

Abstract: A device is provided. The device includes a first Pancharatnam-Berry phase (“PBP”) lens, and a second PBP lens stacked with the first PBP lens. Each of the first PBP lens and the second PBP lens includes a liquid crystal (“LC”) layer. Each side of the LC layer is provided with a continuous electrode and a plurality of patterned electrodes. The patterned electrodes in the first PBP lens are arranged non-parallel to the patterned electrodes in the second PBP lens.

Abstract: The present specification discloses video matching. In a computer-implemented method, a plurality of feature vectors of a target video is obtained. A candidate video similar to the target video is retrieved from a video database based on the plurality of feature vectors of the target video. A time domain similarity matrix feature map is constructed between the target video and the candidate video based on the target video and the candidate video. Using the time domain similarity matrix feature map as an input into a deep learning detection model, a video segment matching the target video in the candidate video and a corresponding similarity is output.

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Abstract: Described herein are KAT6A inhibitors and pharmaceutical compositions comprising said inhibitors. The subject compounds and compositions are useful for the treatment of a disease or disorder associated with KAT6A.

Abstract: Provided is a system for testing a machine learning (ML) model based on simulations in an offline environment that includes at least one processor programmed or configured to receive historical transaction data, generate online simulation data, wherein generating the online simulation data includes modifying the historical timestamp of each data record to provide online simulation data. The processor is further programmed or configured to determine a timeline for a plurality of data insertion actions and a plurality of data request actions based on the online simulation data, perform a simulation of online activities involving a stateful ML model using the timeline for the plurality of data insertion actions and the plurality of data request actions, and validate the stateful ML model based on the simulation of online activities. Methods and computer program products are also provided.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate, a semiconductor chip disposed over the package substrate, and an integrated device located below and bonded to the lower surface of the semiconductor chip. The semiconductor chip has a lower surface facing the package substrate and is electrically connected to the package substrate through conductive structures. The integrated device is laterally surrounded by the conductive structures, and the integrated device and the conductive structures are located within boundaries of the semiconductor chip when viewed in a direction perpendicular to the lower surface of the semiconductor chip.

Abstract: Disclosed are an application start method and an electronic device. The method includes: obtaining, by a SystemServer process in an electronic device, a start message of a first application; sending, by the SystemServer process, a creation request for an application process to a daemon process in response to the start message, where the creation request includes application information of the first application; creating, by the daemon process, the application process for the first application in response to the creation request, where the application process includes a first thread and a second thread; executing, by the application process, the first thread and the second thread in parallel, where the first thread executes initialization of a main thread of the first application, and the second thread creates a first class loader according to the application information to load a class file of the first application.