Patents by Inventor Feng-Cheng Hsu

Feng-Cheng Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220246579
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Patent number: 11404394
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate, a semiconductor chip over the package substrate, and at least one integrated device integrated with the semiconductor chip. The integrated device is integrated directly beneath the semiconductor chip in order to facilitate signal transmission.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Cheng Hsu, Shin-Puu Jeng, Shuo-Mao Chen
  • Patent number: 11393746
    Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Po-Yao Lin, Shuo-Mao Chen, Feng-Cheng Hsu, Shin-Puu Jeng
  • Publication number: 20220223424
    Abstract: A method of forming a package structure includes the following steps. A first package structure is formed. The first package structure is connected to a second package structure. The method of forming the first package structure includes the following steps. A redistribution layer (RDL) structure is formed. A die is bonded to the RDL structure. The RDL structure is electrically connected to the die. A through via is formed on the RDL structure and laterally aside the die. An encapsulant is formed to laterally encapsulate the through via and the die. A protection layer is formed over the encapsulant and the die. A cap is formed on the through via and laterally aside the protection layer, wherein the cap has a top surface higher than a top surface of the encapsulant and lower than a top surface of the protection layer. The cap is removed from the first package structure.
    Type: Application
    Filed: March 31, 2022
    Publication date: July 14, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng
  • Publication number: 20220223689
    Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 14, 2022
    Inventors: Tzu-Hsiang Hsu, Ting-Yeh Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11387183
    Abstract: A semiconductor device including an integrated circuit, a dielectric layer, a plurality of connecting terminals and at least one dummy conductor is provided. The integrated circuit has a plurality of connecting pads, and the dielectric layer is disposed thereon and partially exposes the plurality of the connecting pads by a plurality of openings defined therein. The plurality of the connecting terminals is disposed on the plurality of the connecting pads exposed by the plurality of the openings. The at least one dummy conductor is disposed on the dielectric layer and electrically isolated from the integrated circuit. A substantial topology variation is between the plurality of the connecting terminals and the at least one dummy conductor. A semiconductor package having the semiconductor device is also provided.
    Type: Grant
    Filed: May 10, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Cheng Hsu, Shin-Puu Jeng
  • Publication number: 20220181232
    Abstract: A method for forming a package structure is provided, including forming an interconnect structure over a carrier substrate and forming a semiconductor die over a first side of the interconnect structure. A removable film is formed over the semiconductor die. The method includes forming a first stacked die package structure over the first side of the interconnect structure. A top surface of the removable film is higher than a top surface of the first stacked die package structure. The method includes forming a package layer, removing a portion of the package layer to expose a portion of the removable film, removing the removable film to form a recess, forming a lid structure over the semiconductor die and the first stacked die package structure. The lid structure has a main portion and a protruding portion disposed in the recess and extending from the main portion.
    Type: Application
    Filed: February 24, 2022
    Publication date: June 9, 2022
    Inventors: Shin-Puu JENG, Po-Yao LIN, Feng-Cheng HSU, Shuo-Mao CHEN, Chin-Hua WANG
  • Patent number: 11355474
    Abstract: A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via.
    Type: Grant
    Filed: June 20, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Cheng Hsu, Shin-Puu Jeng
  • Publication number: 20220165587
    Abstract: An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.
    Type: Application
    Filed: February 10, 2022
    Publication date: May 26, 2022
    Inventors: Feng-Cheng Hsu, Shuo-Mao Chen, Jui-Pin Hung, Shin-Puu Jeng
  • Patent number: 11342255
    Abstract: A semiconductor package device includes an interposer die having a semiconductor substrate and a plurality of through-silicon-vias (TSVs) extending through the semiconductor substrate. The semiconductor package device also includes a first semiconductor die spaced apart from the interposer die, a first redistribution layer disposed on a first side of the interposer die and electrically coupling the interposer die with the first semiconductor die, and a second redistribution layer on a second side of the interposer die opposite the first side. Each of the plurality of TSVs includes a sidewall tapering from a first end near the second redistribution layer to a second end near the first redistribution layer.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Shin-Puu Jeng
  • Patent number: 11342306
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Grant
    Filed: August 30, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Patent number: 11335672
    Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
  • Publication number: 20220108967
    Abstract: A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive bump connected between the first chip and the first redistribution structure. The chip package structure includes a first conductive pillar over the first surface and electrically connected to the first redistribution structure. The chip package structure includes a second chip over the second surface. The chip package structure includes a second conductive bump connected between the second chip and the first redistribution structure. The chip package structure includes a second conductive pillar over the second surface and electrically connected to the first redistribution structure.
    Type: Application
    Filed: December 17, 2021
    Publication date: April 7, 2022
    Inventors: Shin-Puu JENG, Shuo-Mao CHEN, Feng-Cheng HSU
  • Patent number: 11295957
    Abstract: A package structure and method of forming the same are provided. The package structure includes a die, a TIV, an encapsulant, a RDL structure, an underfill layer, a protection layer, and a cap. The TIV is aside the die. The encapsulant laterally encapsulates the die and the TIV. The RDL structure is electrically connected to the die. The underfill layer is disposed between the die and the RDL structure and laterally encapsulated by the encapsulant. The protection layer is overlying the die and the encapsulant. The cap covers a top surface of the TIV and laterally aside the protection layer. A top surface of the cap is higher than a top surface of the encapsulant and lower than a top surface of the protection layer.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng
  • Patent number: 11282759
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate, a first semiconductor device, a second semiconductor device, and a protective layer. The interposer substrate is disposed over the package substrate. The first semiconductor device and the second semiconductor device are disposed over the interposer substrate, wherein the first semiconductor device and the second semiconductor device are different types of electronic devices. The protective layer is formed over the interposer substrate to surround the first semiconductor device and the second semiconductor device. The second semiconductor device is exposed from the protective layer and the first semiconductor device is not exposed from the protective layer.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Cheng Hsu, Shin-Puu Jeng, Shuo-Mao Chen
  • Patent number: 11264300
    Abstract: A package structure and method for forming the same are provided. The package structure includes a semiconductor die formed over a first side of an interconnect structure, and the semiconductor die has a first height. The package structure also includes a first stacked die package structure formed over the first side of the interconnect structure, and the first stacked die package structure has a second height. The second height is greater than the first height. The package structure includes a lid structure formed over the semiconductor die and the first stacked die package structure. The lid includes a main portion and a protruding portion extending from the main portion, and the protruding portion is directly over the semiconductor die.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Puu Jeng, Po-Yao Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Chin-Hua Wang
  • Patent number: 11251142
    Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements. The fabrication methods for forming a package structure are provided.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
  • Patent number: 11251054
    Abstract: An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Cheng Hsu, Shuo-Mao Chen, Jui-Pin Hung, Shin-Puu Jeng
  • Patent number: 11239194
    Abstract: A chip package structure is provided. The chip package structure includes a first redistribution structure including a dielectric structure and wiring layers in the dielectric structure. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive pillar over the first surface and electrically connected to the wiring layers. The chip package structure includes a second chip over the second surface. The second chip includes a second substrate and a second conductive pad over the second substrate, and the second conductive pad is between the second substrate and the first redistribution structure. The chip package structure includes a second conductive pillar over the second surface and electrically connected to the wiring layers.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Feng-Cheng Hsu
  • Patent number: 11205603
    Abstract: A semiconductor package including at least one integrated circuit component and a glue material is provided. The at least one integrated circuit component has a top surface with conductive terminals and a backside surface opposite to the top surface. The glue material encapsulates the at least one integrated circuit component, wherein a first lateral thickness of the glue material is smaller than a second lateral thickness of the glue material, the second lateral thickness is parallel to the first lateral thickness, and the first lateral thickness is substantially coplanar with the top surface.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Cheng Hsu, Shin-Puu Jeng