Abstract: A pixel sensor includes a transistor between a transfer transistor on a first semiconductor die and a source-follower gate on a second semiconductor die. The arrangement of the transistor may reduce input capacitance to the source-follower gate, which results in increased conversion gain in low-lighting conditions (e.g., high conversion gain mode) of a multiple semiconductor die image sensor device. A transistor between a first floating diffusion node coupled to the transfer transistor, and a second floating diffusion node coupled to the source-follower gate, may be turned off during signal readout from the source-follower gate, which blocks the signal path between the transistor and the transfer transistor. This prevents parasitic capacitance from the signal path from delaying and/or reducing the discharge of photocurrent from the second floating diffusion node onto the source-follower gate. As a result, substantially the full magnitude of the photocurrent can be applied to the source-follower gate.

Abstract: In some embodiments, the present disclosure relates to a method for forming an image sensor and associated device structure. A backside deep trench isolation (BDTI) structure is formed in a substrate separating a plurality of pixel regions. The BDTI structure encloses a plurality of photodiodes and comprising a first BDTI component arranged at a crossroad of the plurality of pixel regions and a second BDTI component arranged at remaining peripheries of the plurality of pixel regions. The first BDTI component has a first depth from a backside of the substrate smaller than a second depth of the second BDTI component.

Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.

Abstract: In some embodiments, the present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a floating diffusion node disposed within a substrate. A plurality of photodetectors are disposed around the floating diffusion node, as viewed in a plan-view, and a plurality of transfer transistor gates are disposed between the floating diffusion node and the plurality of photodetectors, as viewed in the plan-view. One or more transistor gates are disposed on the substrate. A device isolation structure extends in a closed loop around the one or more transistor gates. The device isolation structure is laterally offset from the floating diffusion node.

Abstract: A photosensing pixel includes a substrate, a photosensing region, a floating diffusion region, a transfer gate and a control electrode. The photosensing region is located within the substrate. The floating diffusion region is located within the substrate aside the photosensing region. The transfer gate is disposed on the substrate and extending into the photosensing region. The control electrode is located on the substrate and extending into the floating diffusion region.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate having a device region with one or more semiconductor devices. The substrate has one or more interior surfaces that form one or more trenches within the substrate along opposing sides of the device region. A multi-layer film stack is disposed along the one or more interior surfaces of the substrate. A core material is arranged within the one or more trenches and is surrounded by the multi-layer film stack. The multi-layer film stack includes a plurality of dielectric material respectively having different electron affinities. The plurality of dielectric materials are arranged to form one or more potential wells within the multi-layer film stack.

Abstract: An integrated chip includes a photodetector, a transfer transistor, a first pixel transistor, a capacitor, a second pixel transistor, and a bonding structure. A first terminal of the transfer transistor is coupled to a first terminal of the photodetector. The first pixel transistor is on a first semiconductor chip. A first terminal of the first pixel transistor is coupled to a second terminal of the transfer transistor. The capacitor is on the first semiconductor chip. A first terminal of the capacitor is coupled to a second terminal of the first pixel transistor. The second pixel transistor is on a second semiconductor chip bonded to the first semiconductor chip. The bonding structure is at an interface where the first semiconductor chip and the second semiconductor chip are bonded together. The bonding structure couples the second terminal of the capacitor to the first terminal of the second pixel transistor.

Abstract: A semiconductor die of an image sensor device includes a doped well region in a substrate layer of the semiconductor die. The doped well region may be included adjacent to an elongated conductive structure that extends vertically through the substrate layer into interconnect layers on opposing sides of the substrate layer. The doped well region introduces additional series capacitance between the elongated conductive structure and the substrate layer (which may be formed of one or more semiconductor materials). This additional series capacitance, which is electrically connected in series with parasitic capacitance associated with the elongated conductive structure, effectively reduces the overall parasitic capacitance in the control circuitry of the pixel sensors of the image sensor device.

Abstract: Some embodiments relate to a pixel array, including: a substrate; a plurality of photodetectors within the substrate; a deep trench isolation (DTI) structure with segments extending between photodetectors of the plurality of photodetectors, the DTI structure comprising: a first oxide layer having a first oxygen density; a first metal oxide layer lining inner sidewalls of the first oxide layer and having a second oxygen density greater than the first oxygen density; a second oxide layer lining inner sidewalls of the first metal oxide layer and having a third oxygen density less than the second oxygen density; and a second metal oxide layer lining inner sidewalls of the second oxide layer and having a fourth oxygen density greater than the third oxygen density.

Abstract: A photosensing pixel includes a substrate, a photosensing region, a floating diffusion region, a transfer gate and a control electrode. The photosensing region is located within the substrate. The floating diffusion region is located within the substrate aside the photosensing region. The transfer gate is disposed on the substrate and extending into the photosensing region. The control electrode is located on the substrate and extending into the floating diffusion region.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a plurality of photodetectors disposed within a substrate. The photodetectors are disposed respectively within a plurality of pixel regions. A floating diffusion node is disposed along a front-side surface of the substrate at a middle region of the plurality of pixel regions. A plurality of well regions is disposed within the substrate at corners of the plurality of pixel regions. An isolation structure extends into a back-side surface of the substrate. The isolation structure comprises a plurality of elongated isolation components disposed between adjacent pixel regions, a middle isolation component aligned with the floating diffusion node, and multiple peripheral isolation components aligned with the plurality of well regions. The elongated isolation components have a first height and the middle and peripheral isolation components have a second height less than the first height.

Abstract: A control circuitry region of a pixel sensor of a semiconductor device includes a plurality of conversion gain circuits that may be selectively activated and/or deactivated in various combinations to enable a plurality of sequential conversion gain operations to be performed across an exposure operation of the semiconductor device. The control circuitry region may include a first conversion gain circuit and a second conversion gain circuit that are connected to a floating diffusion node of the pixel sensor in parallel. The selectable parallel conversion gain circuits enable sequential conversion gain operations to be performed for the pixel sensor such that the capacitance in the pixel sensor may be gradually increased through the conversion gain operations. Gradually increasing the capacitance in the pixel sensor across the sequential conversion gain operations provides for smaller signal-to-noise ratio (SNR) drops, which enables a low SNR drop to be achieved for the pixel sensor.

Abstract: An image sensor having a quad pixel structure has a quad pixel circuit including four photodetector pixel circuits and a bridge circuit. The bridge circuit selectively couples the floating diffusion nodes corresponding to the four photodetector pixels and allows the four photodetector pixel circuits to operate selectively in either a quad pixel mode, a dual pixel mode, or a single pixel mode. Each of the photodetector pixel circuits may include a multiple conversion gain circuit to provide a wide dynamic range.

Abstract: Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.

Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.

Abstract: An optical device and a method of fabricating the same are disclosed. The optical device includes a first die layer and a second die layer. The first die layer includes a first substrate having a first surface and a second surface opposite to the first surface, first and second pixel structures, an inter-pixel isolation structure disposed in the first substrate and surrounding the first and second pixel structures, and a floating diffusion region disposed in the first substrate and between the first and second pixel structures. The second die layer includes a second substrate having a third surface and a fourth surface opposite to the third surface and a pixel transistor group disposed on the third surface of the second substrate and electrically connected to the first and second pixel structures.

Abstract: Image sensors and methods for forming the same are provided. A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.

Abstract: A semiconductor device includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, and a redistribution layer over the interconnect structure. The redistribution layer includes bonding vias arranged in a plurality of arrays with rows each extending along a first direction and columns each extending along a second direction. Across the redistribution layer, a ratio of a total number of the columns of the arrays along the first direction over a total number of the rows of the arrays along the second direction ranges from about 0.5 to about 1.5.

Abstract: Some embodiments relate to a device, including: a photodetector; and a pixel circuit, comprising: a floating diffusion node and an output node; a transfer transistor electrically coupled from the floating diffusion node to the photodetector; a source follower transistor comprising a gate electrode electrically coupled to the floating diffusion node; a row select transistor electrically coupled from a source/drain region of the source follower transistor to the output node; and a capacitor electrically coupled from the output node to the floating diffusion node.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a plurality of gate structures arranged along a first side of a substrate within a plurality of pixel regions. An etch block structure is arranged on the first side of the substrate between neighboring ones of the plurality of gate structures. A contact etch stop layer (CESL) is arranged on the etch block structure between the neighboring ones of the plurality of gate structures. An isolation structure is disposed between one or more sidewalls of the substrate and extends from a second side of the substrate to the first side of the substrate. The etch block structure is vertically between the isolation structure and the CESL.