Patents by Inventor Feng-Chi Hung
Feng-Chi Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973101Abstract: An image-sensor device is provided. The image-sensor device includes a semiconductor substrate and a radiation-sensing region in the semiconductor substrate. The image-sensor device also includes a doped isolation region in the semiconductor substrate and a dielectric film extending into the doped isolation region from a surface of the semiconductor substrate. A portion of the doped isolation region is between the dielectric film and the radiation-sensing region.Type: GrantFiled: May 23, 2022Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung
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Patent number: 11923338Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.Type: GrantFiled: April 20, 2020Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Ying Ho, Jeng-Shyan Lin, Wen-I Hsu, Feng-Chi Hung, Dun-Nian Yaung, Ying-Ling Tsai
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Patent number: 11915977Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.Type: GrantFiled: April 12, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
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Patent number: 11908878Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.Type: GrantFiled: May 24, 2021Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Sheng-Chau Chen, Feng-Chi Hung, Sheng-Chan Li
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Patent number: 11901387Abstract: A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.Type: GrantFiled: July 7, 2021Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Sheng-Chau Chen, Feng-Chi Hung, Sheng-Chan Li
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Patent number: 11894410Abstract: Some embodiments relate an integrated circuit (IC) including a first substrate including a plurality of imaging devices. A second substrate is disposed under the first substrate and includes a plurality of logic devices. A first interconnect structure is disposed between the first substrate and the second substrate and electrically couples imaging devices within the first substrate to one another. A second interconnect structure is disposed between the first interconnect structure and the second substrate, and electrically couples logic devices within the second substrate to one another. A bond pad structure is coupled to a metal layer of the second interconnect structure and extends along inner sidewalls of both the first interconnect structure and the second interconnect structure. An oxide layer extends from above the first substrate to below a plurality of metal layers of the first interconnect structure, and lines inner sidewalls of the bond pad structure.Type: GrantFiled: February 1, 2022Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sin-Yao Huang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Ming-Tsong Wang, Shih Pei Chou
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Publication number: 20240030261Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a plurality of photodetectors disposed within a substrate. The photodetectors are disposed respectively within a plurality of pixel regions. A floating diffusion node is disposed along a front-side surface of the substrate at a middle region of the plurality of pixel regions. A plurality of well regions is disposed within the substrate at corners of the plurality of pixel regions. An isolation structure extends into a back-side surface of the substrate. The isolation structure comprises a plurality of elongated isolation components disposed between adjacent pixel regions, a middle isolation component aligned with the floating diffusion node, and multiple peripheral isolation components aligned with the plurality of well regions. The elongated isolation components have a first height and the middle and peripheral isolation components have a second height less than the first height.Type: ApplicationFiled: January 5, 2023Publication date: January 25, 2024Inventors: Wen-I Hsu, Hsin-Hung Chen, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Wen-Chang Kuo
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Publication number: 20240021643Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.Type: ApplicationFiled: July 21, 2023Publication date: January 18, 2024Inventors: Wei Chuang Wu, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Jhy-Jyi Sze, Keng-Yu Chou, Yen-Ting Chiang, Ming-Hsien Yang, Chun-Yuan Chen
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Publication number: 20240021641Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor comprise a substrate having a first region and a second region. A first gate overlies the first region. A second gate overlies the second region. A deep trench isolation (DTI) structure is in the substrate and laterally between the first region and the second region. A first floating diffusion node is in the first region. A second floating diffusion node is in the second region. An interlayer dielectric (ILD) structure is over the substrate. A dielectric structure is between the ILD structure and the substrate. The dielectric structure is laterally between the first and second floating diffusion nodes. The dielectric structure is laterally spaced from the first and second gates. The dielectric structure overlies the DTI structure. A width of the dielectric structure is greater than a width of the DTI structure.Type: ApplicationFiled: January 4, 2023Publication date: January 18, 2024Inventors: Wei Long Chen, Wen-I Hsu, Feng-Chi Hung, Jen-Cheng Liu, Dun-Nian Yaung
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Publication number: 20230420464Abstract: The present disclosure relates to semiconductor device with a multi-gate structure. The semiconductor device includes a substrate and a doped region disposed within the substrate. A gate electrode is disposed over the doped region, and a source region and a drain region are disposed within the doped region. A shallow trench isolation (STI) structure is disposed within the substrate and laterally surrounds the source region and the drain region. A first doped liner is disposed along the STI structure, where the first doped liner separates the STI structure from the source region and the drain region. A second doped liner is disposed along the STI structure, where the second doped liner is separated from the first doped liner by the STI structure above a bottom surface of the STI structure.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Inventors: Chih-Kuan Yu, Shen-Hui Hong, Feng-Chi Hung, Wen-I Hsu, Jen-Cheng Liu, Dun-Nian Yaung
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Publication number: 20230395631Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.Type: ApplicationFiled: August 9, 2023Publication date: December 7, 2023Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Sheng-Chau Chen, Feng-Chi Hung, Sheng-Chan Li
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Publication number: 20230361149Abstract: In some embodiments, the present disclosure relates to a method for forming an image sensor and associated device structure. A backside deep trench isolation (BDTI) structure is formed in a substrate separating a plurality of pixel regions. The BDTI structure encloses a plurality of photodiodes and comprising a first BDTI component arranged at a crossroad of the plurality of pixel regions and a second BDTI component arranged at remaining peripheries of the plurality of pixel regions. The first BDTI component has a first depth from a backside of the substrate smaller than a second depth of the second BDTI component.Type: ApplicationFiled: August 8, 2022Publication date: November 9, 2023Inventors: Hsin-Hung Chen, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Wen-Chang Kuo, Hung-Wen Hsu, Shih-Chang Liu
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Publication number: 20230361085Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first integrated chip (IC) tier and a second IC tier. The second IC tier comprises a second plurality of conductors within a second insulating structure disposed on the second semiconductor body. A conductive pad is electrically coupled to the second plurality of conductors and has a conductive surface available to a side of the second semiconductor body facing away from the first semiconductor body. The IC first tier contacts the second IC tier along a bonding interface including one or more conductive regions and one or more insulating regions. The one or more conductive regions laterally outside of a bottom surface of the conductive pad.Type: ApplicationFiled: July 20, 2023Publication date: November 9, 2023Inventors: Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Sheng-Chau Chen, Dun-Nian Yaung, Feng-Chi Hung, Yung-Lung Lin
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Publication number: 20230361143Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.Type: ApplicationFiled: July 20, 2023Publication date: November 9, 2023Inventors: Feng-Chi Hung, Dun-Nian Yaung, Jen-Cheng Liu, Wei Chuang Wu, Yen-Yu Chen, Chih-Kuan Yu
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Patent number: 11804473Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects arranged within a first inter-level dielectric (ILD) structure on a first substrate, and a second plurality of interconnects arranged within a second ILD structure between the first ILD structure and a second substrate. A bonding structure is disposed within a recess extending through the second substrate. A connector structure is vertically between the first plurality of interconnects and the second plurality of interconnects. The second plurality of interconnects include a first interconnect directly contacting the bonding structure. The second plurality of interconnects also include one or more extensions extending from directly below the first interconnect to laterally outside of the first interconnect and directly above the connector structure, as viewed along a cross-sectional view.Type: GrantFiled: May 28, 2021Date of Patent: October 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Sheng-Chau Chen, Dun-Nian Yaung, Feng-Chi Hung, Yung-Lung Lin
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Patent number: 11791357Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.Type: GrantFiled: August 4, 2021Date of Patent: October 17, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Chuang Wu, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Jhy-Jyi Sze, Keng-Yu Chou, Yen-Ting Chiang, Ming-Hsien Yang, Chun-Yuan Chen
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Patent number: 11791361Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.Type: GrantFiled: July 19, 2022Date of Patent: October 17, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Chi Hung, Dun-Nian Yaung, Jen-Cheng Liu, Wei Chuang Wu, Yen-Yu Chen, Chih-Kuan Yu
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Publication number: 20230317757Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a plurality of photodetectors disposed within a substrate. The substrate comprises a front-side surface opposite a back-side surface. An outer isolation structure is disposed in the substrate and laterally surrounds the plurality of photodetectors. The outer isolation structure has a first height. An inner isolation structure is spaced between sidewalls of the outer isolation structure. The inner isolation structure is disposed between adjacent photodetectors in the plurality of photodetectors. The outer isolation structure and the inner isolation structure respectively extend from the back-side surface toward the front-side surface. The inner isolation structure comprises a second height less than the first height.Type: ApplicationFiled: May 31, 2022Publication date: October 5, 2023Inventors: Yen-Ting Chiang, Yen-Yu Chen, Wen Hao Chang, Tzu-Hsuan Hsu, Feng-Chi Hung, Shyh-Fann Ting, Jen-Cheng Liu
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Publication number: 20230275109Abstract: A semiconductor image sensing structure includes a substrate having a first region and a second region, a metal grid in the first region, and a hybrid metal shield in the second region. The hybrid metal shield includes a first metallization layer, a second metallization layer disposed over the first metallization layer, a third metallization layer disposed over the second metallization layer, and a fourth metallization layer disposed over the third metallization layer. An included angle of the second metallization layer is between approximately 40° and approximately 60°.Type: ApplicationFiled: January 28, 2022Publication date: August 31, 2023Inventors: MING-HSIEN YANG, WEN-I HSU, KUAN-FU LU, FENG-CHI HUNG, JEN-CHENG LIU, DUN-NIAN YAUNG, CHUN-HAO CHOU, KUO-CHENG LEE
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Publication number: 20230201613Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung