Abstract: A wire-OR matching circuit with low power consumption can be enabled by inputting an input-enabling signal representing “enabled.” The wire-OR matching circuit generates an output-enabling signal according to a control signal and a periodic pulse signal. When the periodic pulse signal represents “turn on”, if the input-enabling signal represents “enabled” and the control signal represents “not disabled”, the output-enabling signal represents “enabled;” if the input-enabling signal represents “enabled” and the control signal represents “disabled”, the output-enabling signal represents “not enabled.” The wire- or matching circuit can promptly break the connection between the high voltage source and the low voltage source by controlling the pulse width of the periodic pulse signal. In this way, large current is avoided, saving power consumption.

Abstract: A delay lock loop system includes a timing controller, an OR gate, an input buffer, a pulse generator, and a delay lock loop. The timing controller is used for outputting an external enable signal periodically while a power saving signal is at a logic-low voltage, and being disabled according to a logic-high voltage of the power saving signal. The pulse generator is used for generating a pulse according to the positive edge of the power saving signal. The OR gate is coupled to the timing controller for receiving the power saving signal, the pulse, and the external enable signal, and outputting an enable signal according to the power saving signal and the external enable signal. The delay lock loop is coupled to the OR gate and the input buffer for enabling the delay lock loop again according to the enable signal.

Abstract: A method of dynamically adjusting phase-chasing speed for increasing efficiency of a DLL circuit includes detecting an overall loop delay for an input clock signal in the DLL circuit, obtaining an optimal divisor according to the overall loop delay, and in the phase-locking period of the DLL circuit, dividing the frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor.

Abstract: A voltage hold circuit includes four switches, an operational amplifier and a capacitor. By turning the switches on and off, the operational amplifier functions as a unity-gain buffer. In the normal operation mode, the positive input end of the operational amplifier is coupled to a node, and the output end of the operational amplifier is coupled to the capacitor. Thus the voltage of the capacitor is equal to the voltage of the node. In the power off mode, the positive input end of the operational amplifier is coupled d to the capacitor, and the output end of the operational amplifier is coupled to the node. Thus the voltage of the node is equal to the voltage of the capacitor. Therefore, the voltage hold circuit is able to hold the voltage of the node in the power down state.

Abstract: A delay lock loop system includes a timing controller, an OR gate, an input buffer, a pulse generator, and a delay lock loop. The timing controller is used for outputting an external enable signal periodically while a power saving signal is at a logic-low voltage, and being disabled according to a logic-high voltage of the power saving signal. The pulse generator is used for generating a pulse according to the positive edge of the power saving signal. The OR gate is coupled to the timing controller for receiving the power saving signal, the pulse, and the external enable signal, and outputting an enable signal according to the power saving signal and the external enable signal. The delay lock loop is coupled to the OR gate and the input buffer for enabling the delay lock loop again according to the enable signal.

Abstract: A regulator includes a first amplifier, a second amplifier, a current control circuit, a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, and a feedback circuit. The current control circuit includes a controller and at least one switch, and a second terminal of the first P-type metal-oxide-semiconductor transistor is coupled to a second terminal of the second P-type metal-oxide-semiconductor transistor. The regulator utilizes the controller to turn off the at least one switch during operation of the regulator in a light load mode, and the regulator utilizes the controller to turn on the at least one switch in turn when the regulator changes from the light load mode to a heavy load mode. Thus, the regulator can quickly recover a load current in the heavy load mode.

Abstract: A voltage hold circuit includes four switches, an operational amplifier and a capacitor. By turning the switches on and off, the operational amplifier functions as a unity-gain buffer. In the normal operation mode, the positive input end of the operational amplifier is coupled to a node, and the output end of the operational amplifier is coupled to the capacitor. Thus the voltage of the capacitor is equal to the voltage of the node. In the power off mode, the positive input end of the operational amplifier is coupled d to the capacitor, and the output end of the operational amplifier is coupled to the node. Thus the voltage of the node is equal to the voltage of the capacitor. Therefore, the voltage hold circuit is able to hold the voltage of the node in the power down state.

Abstract: A wire-OR matching circuit with low power consumption can be enabled by inputting an input-enabling signal representing “enabled.” The wire-OR matching circuit generates an output-enabling signal according to a control signal and a periodic pulse signal. When the periodic pulse signal represents “turn on”, if the input-enabling signal represents “enabled” and the control signal represents “not disabled”, the output-enabling signal represents “enabled;” if the input-enabling signal represents “enabled” and the control signal represents “disabled”, the output-enabling signal represents “not enabled.” The wire- or matching circuit can promptly break the connection between the high voltage source and the low voltage source by controlling the pulse width of the periodic pulse signal. In this way, large current is avoided, saving power consumption.

Abstract: A method of dynamically adjusting phase-chasing speed for increasing efficiency of a DLL circuit includes detecting an overall loop delay for an input clock signal in the DLL circuit, obtaining an optimal divisor according to the overall loop delay, and in the phase-locking period of the DLL circuit, dividing the frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor.

Abstract: PFD includes UP and DOWN signal modules, and RESET signal module. UP and DOWN signal modules transmit UP and DOWN signals according to reference and fed-back clock signals. RESET module includes UP-RESET and DOWN-RESET signal modules. UP-RESET signal module resets UP signal module according to pre-trigger fed-back signal, UP and DOWN signals. Pre-trigger fed-back signal is generated according to original fed-back clock signal and calculation of logic gates and inverting delay module. DOWN-RESET signal module resets DOWN signal module according to pre-trigger reference signal, UP and DOWN signals. Pre-trigger reference signal is generated according to original reference clock signal and calculation of logic gates and inverting delay module.

Abstract: PFD includes UP and DOWN signal modules, and RESET signal module. UP and DOWN signal modules transmit UP and DOWN signals according to reference and fed-back clock signals. RESET module includes UP-RESET and DOWN-RESET signal modules. UP-RESET signal module resets UP signal module according to pre-trigger fed-back signal, UP and DOWN signals. Pre-trigger fed-back signal is generated according to original fed-back clock signal and calculation of logic gates and inverting delay module. DOWN-RESET signal module resets DOWN signal module according to pre-trigger reference signal, UP and DOWN signals. Pre-trigger reference signal is generated according to original reference clock signal and calculation of logic gates and inverting delay module.

Abstract: Constant delay circuit includes signal input end, delay signal output end, RC delay circuit, and a comparator. The signal input end receives an input signal. The delay signal output end outputs the delay input signal, which the delay period is predetermined. The RC delay circuit is coupled to the signal input end for receiving the input signal and generating a voltage. The comparator includes a first input end, a second input end, and an output end. The first end of the comparator is coupled to the RC delay circuit for receiving the voltage. The second end of the comparator receives a reference voltage. The output end of the comparator is coupled to the delay signal output end of the long delay circuit. The comparator compares the reference voltage and the voltage, and accordingly generates a result as the delay signal.