Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, a transistor comprises a source, a drain, and a pair of spacers between the source and the drain. In an embodiment, a semiconductor channel is between the source and the drain, where the semiconductor channel passes through the pair of spacers. In an embodiment, the semiconductor channel has a first thickness within the pair of spacers and a second thickness between the pair of spacers, where the second thickness is less than the first thickness. In an embodiment, the transistor further comprises a gate stack over the semiconductor channel between the pair of spacers.

Abstract: Methods for fabricating an integrated circuit (IC) device with a protection liner between doped semiconductor regions are provided. An example IC device includes a channel material having a first face and a second face opposite the first face, a first doped region and a second doped region in the channel material, extending from the second face towards the first face by a first distance; and an insulator structure in a portion of the channel material between the first and second doped regions, the insulator structure extending from the second face towards the first face by a second distance greater than the first distance. The insulator structure includes a first portion between the second face and the first distance and a second portion between first distance and the second distance. The insulator structure includes a liner material on sidewalls of the first portion but absent on sidewalls of the second portion.

Abstract: Techniques are provided herein to form semiconductor devices having epitaxial growth laterally extending between inner spacer structures to mitigate issues caused by the inner spacer structures either being too thick or too thin. A directional etch is performed along the side of a multilayer fin to create a relatively narrow opening for a source or drain region to increase the usable fin space for forming the inner spacer structures. After the inner spacer structures are formed around ends of the semiconductor layers within the fin, the exposed ends of the semiconductor layers are laterally recessed inwards from the outermost sidewalls of the inner spacer structures. Accordingly, the epitaxial source or drain region is grown from the recessed semiconductor ends and thus fills in the recessed regions between the spacer structures.

Abstract: Fin trim plug structures with metal for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction. A first isolation structure is over a first end of the fin. A gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of a region of the fin. The gate structure is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end, the second isolation structure spaced apart from the gate structure along the direction. The first isolation structure and the second isolation structure both include a dielectric material laterally surrounding an isolated metal structure.

Abstract: Techniques are provided herein to form semiconductor devices that include a layer across an upper surface of a dielectric fill between devices and configured to prevent or otherwise reduce recessing of the dielectric fill. In this manner, the layer may be referred to as a barrier layer or recess-inhibiting layer. The semiconductor regions of the devices extend above a subfin region that may be native to the substrate. These subfin regions are separated from one another using a dielectric fill that acts as a shallow trench isolation (STI) structure to electrically isolate devices from one another. A barrier layer is formed over the dielectric fill early in the fabrication process to prevent or otherwise reduce the dielectric fill from recessing during subsequent processing. The layer may include oxygen and a metal, such as aluminum.

Abstract: A wireless remote control circuit with dual processing units and a method is provided, which includes a signal receiving unit, a first and a second processing unit. The first processing unit is connected to the signal receiving unit and switches between an activation mode and a sleep mode at a predefined time. The second processing unit is connected to the first processing unit and is preset in the sleep mode. The first processing unit provides a voltage to activate the signal receiving unit during the activation mode, and transmits a resume signal after obtaining a control signal. Then, the second processing unit enters an activation mode after it receives the resume signal, and enters the sleep mode again after its internal logic circuit completes its operation, so as to reduce the complexity of using a single processing unit to design a circuit and avoid huge power consumption of the circuit.

Abstract: An infrared thermometer includes a thermal conductor and a thermal adjuster to conduct suitable thermal flux into the sensor unit. A thermal conductive bushing is also mounted under the bottom of the sensor unit and touching the thermal conductor. The thermal fluxes conducting to the upper portion and the lower portion of the sensor unit are thus balanced suitably and quickly to remove the thermal noise and help the thermometer maintaining precise measurements from infrared radiation of the target.

Abstract: An infrared thermometer includes a thermal conductor and a thermal adjuster to conduct suitable thermal flux into the sensor unit. A thermal conductive bushing is also mounted under the bottom of the sensor unit and touching the thermal conductor. The thermal fluxes conducting to the upper portion and the lower portion of the sensor unit are thus balanced suitably and quickly to remove the thermal noise and help the thermometer maintaining precise measurements from infrared radiation of the target.