Patents by Inventor Feng-Chuan Lin

Feng-Chuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080108866
    Abstract: The object of the present invention is to reveal how to control the operation of a capsule endoscope that has a memory storage device. The capsule endoscope is swallowed through the mouth to start the photographic inspection. During the process of operating the capsule endoscope, the built-in wireless receiving module is used to receive instructions and further to adjust the movement of capsule endoscope in order to achieve the inspection tasks; on completion of the photographic inspection, the capsule shell is cut open and connected to the host computer, and the image and data stored in the storage module are accessed through the host computer.
    Type: Application
    Filed: November 6, 2006
    Publication date: May 8, 2008
    Inventor: Feng-Chuan Lin
  • Patent number: 7144799
    Abstract: Disclosed is a method for pre-retaining CB opening in a DRAM manufacture process, wherein a CB opening is filed with a photo-resist layer and an LPD oxidation layer that is filled at room temperature to avoid damaging caused by conventional etching techniques. The LPD oxidation layer and the photo-resist are replaced easily by a polysilicon layer and a BPSG layer.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: December 5, 2006
    Assignee: Nan Ya Technology Corporation
    Inventors: Yinan Chen, Jeng-Ping Lin, Feng-Chuan Lin
  • Publication number: 20060228845
    Abstract: Disclosed is a method for pre-retaining CB opening in a DRAM manufacture process, wherein a CB opening is filed with a photo-resist layer and an LPD oxidation layer that is filled at room temperature to avoid damaging caused by conventional etching techniques. The LPD oxidation layer and the photo-resist are replaced easily by a polysilicon layer and a BPSG layer.
    Type: Application
    Filed: April 6, 2005
    Publication date: October 12, 2006
    Inventors: Yinan Chen, Jeng-Ping Lin, Feng-Chuan Lin
  • Publication number: 20050158972
    Abstract: A method is disclosed for manufacturing bit line contact structures of semiconductor memories. The manufacturing method comprises the steps of providing a semiconductor substrate, forming a plurality of gates on the surface of the substrate, applying a first insulating layer to cover the surface of the substrate and the gates, selectively forming a plurality of gate contact windows at the locations of the gates, selectively forming bit line contact windows in the first insulating layer, the bit line contact windows contacting the substrate, and filling the gate contact windows and the bit line contact windows with a conductive layer.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Applicant: Nanya Technology Corporation
    Inventors: Feng-Chuan Lin, Yi-Nan Chen, Ping Hsu
  • Patent number: 6872619
    Abstract: A method for forming a semiconductor device having a trench top isolation layer. A collar insulating layer is formed over a lower portion of the sidewall of the trench formed in a substrate. A first conductive layer is formed in the lower portion of the trench and protrudes the collar insulating layer, and a second conductive layer is formed overlying the first conductive layer and covers the collar insulating layer. An insulating spacer is formed over an upper portion of the sidewall of the trench and separated from the second conductive layer by a gap. The second conductive layer is partially thermally oxidized to form an oxide layer thereon whereby the gap is filled. After the oxide layer is removed, a reverse T-shaped insulating layer is formed thereon by chemical vapor deposition to serve as a trench top isolation layer. Finally, the insulating spacer is removed.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: March 29, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Yi-Nan Chen, Tieh-Chiang Wu, Feng-Chuan Lin
  • Publication number: 20040209422
    Abstract: A method for forming a semiconductor device having a trench top isolation layer. A collar insulating layer is formed over a lower portion of the sidewall of the trench formed in a substrate. A first conductive layer is formed in the lower portion of the trench and protrudes the collar insulating layer, and a second conductive layer is formed overlying the first conductive layer and covers the collar insulating layer. An insulating spacer is formed over an upper portion of the sidewall of the trench and separated from the second conductive layer by a gap. The second conductive layer is partially thermally oxidized to form an oxide layer thereon whereby the gap is filled. After the oxide layer is removed, a reverse T-shaped insulating layer is formed thereon by chemical vapor deposition to serve as a trench top isolation layer. Finally, the insulating spacer is removed.
    Type: Application
    Filed: July 16, 2003
    Publication date: October 21, 2004
    Applicant: Nanya Technology Corporation
    Inventors: Yi-Nan Chen, Tieh-Chiang Wu, Feng-Chuan Lin