Patents by Inventor Feng (Dan) Lin
Feng (Dan) Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7830194Abstract: A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is disclosed. The synchronous circuit is configured to selectively use either a reference clock or its inverted version as the clock signal input to the delay line based on a relationship among the phases of the reference clock, the inverted reference clock, and a feedback clock (generated at the output of the delay line). A delayed version of the feedback clock may be used during determination of the phase relationship. The selective use of the opposite phase of the reference clock for the input of the delay line results in centralization of the lock point for most cases as well as improvement in the tuning range and the time to establish the initial lock, without requiring an additional delay line.Type: GrantFiled: July 11, 2006Date of Patent: November 9, 2010Assignee: Round Rock Research, LLCInventor: Feng (Dan) Lin
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Patent number: 7660187Abstract: A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an array of storage cells, both the read clock and the control clock each being comprised of clock pulses. A value is preloaded into one or both of a first counter located in the read clock domain and a second counter located in the control clock domain such that the difference in starting counts between the two counters is equal to a column address strobe latency (L) minus a synchronization (SP) overhead. A start signal is generated for initiating production of a running count of the read clock pulses in the first counter. The input of the start signal to the second counter is delayed so as to delay the initiation of a running count of the control clock pulses. A value of the second counter is held in response to a read command.Type: GrantFiled: December 8, 2008Date of Patent: February 9, 2010Assignee: Micron Technology, Inc.Inventors: James Brian Johnson, Brent Keeth, Feng Dan Lin
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Publication number: 20090141571Abstract: A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an array of storage cells, both the read clock and the control clock each being comprised of clock pulses. A value is preloaded into one or both of a first counter located in the read clock domain and a second counter located in the control clock domain such that the difference in starting counts between the two counters is equal to a column address strobe latency (L) minus a synchronization (SP) overhead. A start signal is generated for initiating production of a running count of the read clock pulses in the first counter. The input of the start signal to the second counter is delayed so as to delay the initiation of a running count of the control clock pulses. A value of the second counter is held in response to a read command.Type: ApplicationFiled: December 8, 2008Publication date: June 4, 2009Inventors: James Brian Johnson, Brent Keeth, Feng Dan Lin
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Patent number: 7480203Abstract: A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock.Type: GrantFiled: February 22, 2008Date of Patent: January 20, 2009Assignee: Micron Technology, Inc.Inventors: James Brian Johnson, Brent Keeth, Feng (Dan) Lin
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Publication number: 20080225630Abstract: A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock.Type: ApplicationFiled: February 22, 2008Publication date: September 18, 2008Inventors: James Brian Johnson, Brent Keeth, Feng Dan Lin
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Patent number: 7355922Abstract: A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock.Type: GrantFiled: May 8, 2006Date of Patent: April 8, 2008Assignee: Micron Technology, Inc.Inventors: James Brian Johnson, Brent Keeth, Feng (Dan) Lin
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Patent number: 7332946Abstract: Power detection circuitry that provides a substantially constant trip-point is provided. The circuitry is immune to temperature and process variations, thus preventing premature or delayed enablement of utilization circuitry (e.g., memory). In addition, the trip-point remains constant during both slow and fast power up and power down conditions. This may be accomplished with the use of bandgap reference circuitry that provides a stable bandgap reference voltage when operating in its stable operating region. The bandgap circuitry operates in conjunction with startup circuitry, which enables the bandgap circuitry to operate in its non-stable operating region. When in the non-stable region, the bandgap circuitry provides a source voltage as the reference voltage until the source voltage begins to approach the bandgap voltage, at which point the bandgap circuitry provides the stable bandgap reference voltage as the reference voltage.Type: GrantFiled: August 8, 2006Date of Patent: February 19, 2008Assignee: Micron Technology, Inc.Inventors: Dong Pan, Feng (Dan) Lin, Paul A Silvestri
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Publication number: 20070057716Abstract: Power detection circuitry that provides a substantially constant trip-point is provided. The circuitry is immune to temperature and process variations, thus preventing premature or delayed enablement of utilization circuitry (e.g., memory). In addition, the trip-point remains constant during both slow and fast power up and power down conditions. This may be accomplished with the use of bandgap reference circuitry that provides a stable bandgap reference voltage when operating in its stable operating region. The bandgap circuitry operates in conjunction with startup circuitry, which enables the bandgap circuitry to operate in its non-stable operating region. When in the non-stable region, the bandgap circuitry provides a source voltage as the reference voltage until the source voltage begins to approach the bandgap voltage, at which point the bandgap circuitry provides the stable bandgap reference voltage as the reference voltage.Type: ApplicationFiled: August 8, 2006Publication date: March 15, 2007Inventors: Dong Pan, Feng (Dan) Lin, Paul Silvestri
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Patent number: 7148742Abstract: Power detection circuitry that provides a substantially constant trip-point is provided. The circuitry is immune to temperature and process variations, thus preventing premature or delayed enablement of utilization circuitry (e.g., memory). In addition, the trip-point remains constant during both slow and fast power up and power down conditions. This may be accomplished with the use of bandgap reference circuitry that provides a stable bandgap reference voltage when operating in its stable operating region. The bandgap circuitry operates in conjunction with startup circuitry, which enables the bandgap circuitry to operate in its non-stable operating region. When in the non-stable region, the bandgap circuitry provides a source voltage as the reference voltage until the source voltage begins to approach the bandgap voltage, at which point the bandgap circuitry provides the stable bandgap reference voltage as the reference voltage.Type: GrantFiled: July 7, 2004Date of Patent: December 12, 2006Assignee: Micron Technology, Inc.Inventors: Dong Pan, Feng (Dan) Lin, Paul A Silvestri
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Publication number: 20060198237Abstract: A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock.Type: ApplicationFiled: May 8, 2006Publication date: September 7, 2006Inventors: James Johnson, Brent Keeth, Feng (Dan) Lin
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Patent number: 7098714Abstract: A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is disclosed. The synchronous circuit is configured to selectively use either a reference clock or its inverted version as the clock signal input to the delay line based on a relationship among the phases of the reference clock, the inverted reference clock, and a feedback clock (generated at the output of the delay line). A delayed version of the feedback clock may be used during determination of the phase relationship. The selective use of the opposite phase of the reference clock for the input of the delay line results in centralization of the lock point for most cases as well as improvement in the tuning range and the time to establish the initial lock, without requiring an additional delay line.Type: GrantFiled: December 8, 2003Date of Patent: August 29, 2006Assignee: Micron Technology, Inc.Inventor: Feng Dan Lin
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Patent number: 7065001Abstract: A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock.Type: GrantFiled: August 4, 2004Date of Patent: June 20, 2006Assignee: Micron Technology, Inc.Inventors: James Brian Johnson, Brent Keeth, Feng (Dan) Lin
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Publication number: 20060028905Abstract: A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock.Type: ApplicationFiled: August 4, 2004Publication date: February 9, 2006Inventors: James Johnson, Brent Keeth, Feng (Dan) Lin
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Publication number: 20060007616Abstract: Power detection circuitry that provides a substantially constant trip-point is provided. The circuitry is immune to temperature and process variations, thus preventing premature or delayed enablement of utilization circuitry (e.g., memory). In addition, the trip-point remains constant during both slow and fast power up and power down conditions. This may be accomplished with the use of bandgap reference circuitry that provides a stable bandgap reference voltage when operating in its stable operating region. The bandgap circuitry operates in conjunction with startup circuitry, which enables the bandgap circuitry to operate in its non-stable operating region. When in the non-stable region, the bandgap circuitry provides a source voltage as the reference voltage until the source voltage begins to approach the bandgap voltage, at which point the bandgap circuitry provides the stable bandgap reference voltage as the reference voltage.Type: ApplicationFiled: July 7, 2004Publication date: January 12, 2006Inventors: Dong Pan, Feng (Dan) Lin, Paul Silvestri