Abstract: A thin film transistor includes a gate, a gate insulating layer, an active layer, an ionized amorphous silicon layer, a source and a drain. The gate insulating layer covers the gate. The active layer is disposed on a side of the gate insulating layer away from the gate. The ionized amorphous silicon layer is disposed on a side of the active layer away from the gate, and the ionized amorphous silicon layer is in contact with the gate insulating layer. The source and the drain are disposed on a side of the ionized amorphous silicon layer away from the gate insulating layer, and the source and the drain are coupled to the active layer through the ionized amorphous silicon layer.

Abstract: A die bonding apparatus having: a carrier support unit having at least one support element defining a supporting plane and a carrier holder operable to support the carrier panel on a side of the supporting plane with the carrier panel being parallel to the supporting plane, a wafer feed unit having a wafer holder operable to hold a diced wafer in a manner so as to space the diced wafer apart from the supporting plane defined by the at least one support element of the carrier support unit and orient the diced wafer with an exposed surface of the diced wafer facing the side of the supporting plane to which the carrier panel is supported, and a die transfer module disposed between the carrier support unit and the wafer feed unit, the die transfer module operable to transfer a die from the diced wafer to the carrier panel.

Abstract: A display substrate is provided. The display substrate includes a substrate (1), a first transistor (2) and a second transistor (3) on the substrate (1), directions of intrinsic threshold voltage shifts of the first transistor (2) and the second transistor (3) being opposite; and a shift adjustment structure (4) on the substrate (1). The shift adjustment structure (4) may be configured to input adjustment signals to the first transistor (2) and the second transistor (3) respectively to make threshold voltages of the first transistor (2) and the second transistor (3) shift in directions opposite to the directions of their intrinsic threshold voltage shifts respectively.

Abstract: The disclosure relates to a CMOS structure and a manufacturing method thereof. The CMOS structure includes a substrate and an N-type TFT and a P-type TFT on the substrate. The N-type TFT includes a first gate electrode, a first active layer, and a first gate dielectric layer therebetween. The first active layer includes a first semiconductor layer, a second semiconductor layer of the N-type, and a third semiconductor layer of the N-type which are located at opposite ends of the first semiconductor layer and sequentially stacked in a direction away from the first gate dielectric layer. An N-type doping concentration of the second semiconductor layer is smaller than that of the third semiconductor layer. The P-type TFT includes a fifth semiconductor layer and a sixth semiconductor layer. A P-type doping concentration of the fifth semiconductor layer is smaller than that of the sixth semiconductor layer.

Abstract: The present disclosure discloses a method for preparing an array substrate, an array substrate and a display panel, wherein the method comprises: forming a buffer layer on a substrate in a first region and a second region, wherein the buffer layer has a groove located in the second region; forming a first indium oxide thin film on the buffer layer in the first region; forming a second indium oxide thin film in the groove; performing a reduction process on the second indium oxide thin film to obtain indium particles; forming an amorphous silicon thin film in the groove, and inducing the amorphous silicon of the amorphous silicon thin film to form microcrystalline silicon at a preset temperature by using the indium particles; and removing the indium particles in the microcrystalline silicon to form a microcrystalline silicon semiconductor layer of the microcrystalline silicon thin film transistor.

Abstract: A photosensor includes a base substrate; an insulating layer on the base substrate; and a photodiode including a semiconductor junction on a side of the insulating layer away from the base substrate. The semiconductor junction includes a first polarity semiconductor layer, an intrinsic semiconductor layer, and a second polarity semiconductor layer, stacked on the insulating layer. The second polarity semiconductor layer encapsulates a lateral surface of the intrinsic semiconductor layer.

Abstract: The disclosure relates to a CMOS structure and a manufacturing method thereof. The CMOS structure includes a substrate and an N-type TFT and a P-type TFT on the substrate. The N-type TFT includes a first gate electrode, a first active layer, and a first gate dielectric layer therebetween. The first active layer includes a first semiconductor layer, a second semiconductor layer of the N-type, and a third semiconductor layer of the N-type which are located at opposite ends of the first semiconductor layer and sequentially stacked in a direction away from the first gate dielectric layer. An N-type doping concentration of the second semiconductor layer is smaller than that of the third semiconductor layer. The P-type TFT includes a fifth semiconductor layer and a sixth semiconductor layer. A P-type doping concentration of the fifth semiconductor layer is smaller than that of the sixth semiconductor layer.

Abstract: Panel level packaging (PLP) with high positional accuracy of dies. The PLP bonds dies accurately to die bonding regions of an alignment panel. High accuracy is achieved by providing die bonding regions with local alignment marks. Accurate die bonding on the alignment carrier results in a reconstructed wafer with accurate positioning of dies. The dies of the reconstructed wafer can be scanned by a die location check (DLC) scan based on sub-blocks of dies, enabling high DLC throughput. The DLC scan generates a DLC file with coordinate points of sub-blocks of the reconstructed wafer. Also, a laser direct imaging (LDI) file can be generated using sub-block circuit files aligned to the DLC file. The use of sub-block circuit files facilitates high throughput in generating the LDI file with high accuracy due to the reconstructed wafer being formed using the alignment carrier with local alignment marks.

Abstract: The present disclosure discloses a photoelectric detector, a preparation method thereof, a display panel and a display device. The photoelectric detector includes a base, and a thin film transistor (TFT) and a photosensitive PIN device on the base, wherein the PIN device includes an I-type region that does not overlap with an orthographic projection of the TFT on the base; a first etching barrier layer covering a top surface of the I-type region; a first heavily doped region in contact with a side surface on a side, proximate to the TFT, of the I-type region; and a second heavily doped region in contact with a side surface on a side, away from the TFT, of the I-type region, the doping types of the first heavily doped region and the second heavily doped region being different from each other.

Abstract: The present disclosure provides a display backplane and a method for manufacturing the same, a display panel, and a display device. The display backplane includes: a substrate; a first thin film transistor located on one side of the substrate; and a second thin film transistor located on the one side of the substrate, wherein: the first thin film transistor comprises a first active layer, the second thin film transistor comprises a second active layer, wherein the first active layer and the second active layer are located in a same layer, and a material of the first active layer is different from that of the second active layer.

Abstract: A molecular marker for the selection and breeding of fine-wool sheep is disclosed. The marker is an STR marker comprising a (CA)n repeat core sequence, with n between 5 and 24 that can be obtained by PCR amplification of genomic DNA of sheep using the primers shown in SEQ ID NO: 1 and SEQ ID NO: 2 and sequencing the PCR product. When n is 17 or 18, a sheep is a fine-wool breed, and when n is 23 or 24, a sheep is a non-fine-wool breed. When the CA repeat is discontinuous, i.e., divided into two segments (e.g., 12+11 or 13+11) separated by two bases TA or GA, a sheep is a hybrid breed of fine-wool sheep and non-fine-wool sheep. Use of the marker provides methods of identifying of fine-wool sheep breeds, and efficient and accurate selection of fine-wool sheep or the hybrid offspring of fine-wool sheep for breeding.

Abstract: A display substrate, a display apparatus, and a manufacturing method of the display substrate are provided. The display substrate includes: a base substrate; and a crystallization induction layer and a polysilicon layer stacked on the base substrate. The crystallization induction layer includes induction layer patterns and intervals between the induction layer patterns. The polysilicon layer includes a portion overlapping the induction layer patterns and a portion overlapping the intervals, a crystallinity of the portion of the polysilicon layer overlapping the induction layer patterns is larger than a crystallinity of the portion of the polysilicon layer overlapping the intervals.

Abstract: The present disclosure provides a thin film transistor, a pixel structure, a display device, and a manufacturing method. The thin film transistor includes: a gate on the substrate; a gate insulating layer covering the gate and the substrate; a first support portion and a second support portion, which are provided on the gate insulating layer covering the substrate and located on both sides of the gate, wherein the first support portion is not connected to the second support portion; a semiconductor layer on the first support portion, the second support portion, and the gate insulating layer covering the gate; and a source and a drain respectively connected to the semiconductor layer. The first support portion and the second support portion are respectively configured to support the semiconductor layer.

Abstract: A holographic display panel comprises a plurality of display units, each display unit comprises at least two adjacent pixels, each pixel comprises: a plurality of sub-pixels; and a plurality of phase plates. Diffractive angles of light coming out of the phase plates corresponding to the sub-pixels in a same pixel are the same, a diffractive angle of first light coming out of the phase plates corresponding to a first pixel in one of the display units is different from a diffractive angle of second light coming out of the phase plates corresponding to a second pixel that is different from the first pixel but in the same display unit, and a reverse extension line of the first light and a reverse extension line of the second light intersect at an image plane position.

Abstract: The present invention provides a DNA barcode and method for identifying cuttlefishes, mainly depending on the diversity of mitochondrial DNA, including designing universal primers on conservative regions on both sides of the species-specific variable region, amplifying DNA from cuttlefishes, and sequencing PCR products to obtain DNA sequences, and identifying cuttlefish species based on the similarity by comparing with the species information in the database. The method is advantageous in that it can achieve efficient and specific amplification of DNA from such cephalopods as cuttlefishes, with low requirements for necessary instruments and simple operation processes. In addition, the method can be carried out in most molecular biology laboratories, which greatly improves the probability of success of molecular identification for cuttlefishes and sibling species thereof.

Abstract: The present disclosure discloses a silicon-based nanowire, a preparation method thereof, and a thin film transistor. By using a eutectic point of catalyst particles and silicon, and a driving factor that the Gibbs free energy of amorphous silicon is greater than that of crystalline silicon, and due to absorption of the amorphous silicon by the molten catalyst particles to form a supersaturated silicon eutectoid, the silicon nucleates and grows into silicon-based nanowires. Moreover, during the growth of the silicon-based nanowire, the amorphous silicon film grows linearly along guide slots under the action of the catalyst particles, and reverse growth of the silicon-based nanowire is restricted by the retaining walls, thus obtaining silicon-based nanowires with a high density and high uniformity. Furthermore, by controlling the size of the catalyst particles and the thickness of the amorphous silicon film, the width of the silicon-based nanowire may also be controlled.

Abstract: The present disclosure provides a display substrate and a manufacturing method thereof, and a display device. In the display substrate of the present disclosure, a first transistor comprises a first gate electrode, a first electrode, a second electrode, and a first active layer; and a second transistor comprises a second gate electrode, a third electrode, a fourth electrode, and a second active layers, wherein the first active layer comprises a silicon material, the second active layer comprises an oxide semiconductor material, and wherein the third electrode and the first gate electrode are disposed in the same layer, and the fourth electrode and the first electrode, the second electrodes are disposed in the same layer.

Abstract: A display substrate is provided. The display substrate includes a substrate (1), a first transistor (2) and a second transistor (3) on the substrate (1), directions of intrinsic threshold voltage shifts of the first transistor (2) and the second transistor (3) being opposite; and a shift adjustment structure (4) on the substrate (1). The shift adjustment structure (4) may be configured to input adjustment signals to the first transistor (2) and the second transistor (3) respectively to make threshold voltages of the first transistor (2) and the second transistor (3) shift in directions opposite to the directions of their intrinsic threshold voltage shifts respectively.

Abstract: The present disclosure relates to a photodiode, a method for preparing the same, and an electronic device. The photodiode includes: a first electrode layer and a semiconductor structure that are stacked, a surface of the semiconductor structure away from the first electrode layer having a first concave-convex structure; and a second electrode layer arranged on a surface of the semiconductor structure away from the first electrode layer, a surface of the second electrode layer away from the first electrode layer having a second concave-convex structure.

Abstract: A method for manufacturing a display substrate is provided to include: forming an amorphous silicon layer on a base substrate; irradiating at least part of the display region through a mask plate with a laser, to convert a portion of the amorphous silicon layer in the irradiated part of the display region corresponding to channel regions of active layers of transistors into polycrystalline silicon by a laser annealing process; irradiating at least part of the peripheral region with a laser, to convert the amorphous silicon layer in the irradiated part of the peripheral region into polycrystalline silicon; and forming the active layers of the transistors from the amorphous silicon layer which is converted to polycrystalline silicon by a patterning process.