Patents by Inventor Feng Hong

Feng Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11947634
    Abstract: An image object classification method and system are disclosed. The method is executed by a processor coupled to a memory. The method includes: providing an image file including at least one image object, performing a process of extracting multiple binary-classified characteristics on the image object to obtain a plurality of first results independent of each other in categories, combining the plurality of first results in a manner of dimensionality reduction based on concatenation, performing a process of characteristics abstraction on the combined first results to obtain a second result, and performing a process of characteristics integration on the plurality of first results and the second result in a manner of dot product of matrices to obtain a classification result.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: April 2, 2024
    Assignee: Footprintku Inc.
    Inventors: Yan-Jhih Wang, Kuan-Hsiang Tseng, Jun-Qiang Wei, Shih-Feng Huang, Tzung-Pei Hong, Yi-Ting Chen
  • Patent number: 11939666
    Abstract: Methods and apparatus for processing a substrate include cleaning and self-assembly monolayer (SAM) formation for subsequent reverse selective atomic layer deposition. An apparatus may include a process chamber with a processing volume and a substrate support including a pedestal, a remote plasma source fluidly coupled to the process chamber and configured to produce radicals or ionized gas mixture with radicals that flow into the processing volume to remove residue or oxides from a surface of the substrate, a first gas delivery system with a first ampoule configured to provide at least one first chemical into the processing volume to produce a SAM on the surface of the substrate, a heating system located in the pedestal and configured to heat a substrate by flowing gas on a backside of the substrate, and a vacuum system fluidly coupled to the process chamber and configured to control heating of the substrate.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: March 26, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xiangjin Xie, Carmen Leal Cervantes, Feng Chen, Lu Chen, Wenjing Xu, Aravind Kamath, Cheng-Hsiung Matthew Tsai, Tae Hong Ha, Alexander Jansen, Xianmin Tang
  • Publication number: 20240097443
    Abstract: A source-network-load-storage coordination dispatching method in a background of a coupling of renewable energy sources, including: taking an expectation of a minimum grid operating cost in a dispatching cycle as an objective function; generating an approximate value function of an output of a set for generating electricity from renewable energy sources and a user load, and constructing a source-network-load-storage coordination dispatching model with combination of the objective function; obtaining forecast data of the output of a set for generating electricity from renewable energy sources and the user load, and inputting the forecast data into the dispatching model for solving; performing iterative updating on the approximate value function, importing the approximate value function after the iterative updating into the dispatching model for iterative solving, and terminating an iterative process until a solving result satisfies a preset convergence condition; and using a solving result of a last iteration
    Type: Application
    Filed: January 14, 2022
    Publication date: March 21, 2024
    Inventors: Feng Guo, Jian Yang, Lintong Wang, Jiahao Zhou, Yefeng Luo, Dongbo Zhang, Yuande Zheng, Guode Ying, Minzhi Chen, Xinjian Chen, Jie Yu, Weiming Lu, Chi Zhang, Yizhi Zhu, Binren Wang, Chenghuai Hong
  • Publication number: 20240088048
    Abstract: A chip structure provided herein includes a bridge structure including an interconnect bridge, a dielectric layer laterally surrounding the interconnect bridge and through dielectric vias extending from a top of the dielectric layer to a bottom of the dielectric layer, wherein a thickness of the interconnect bridge is identical to a height of each of the through dielectric vias; semiconductor dies disposed on the bridge structure, wherein each of the semiconductor dies overlaps both the interconnect bridge and the dielectric layer and is electrically connected to the interconnect bridge and at least one of the through dielectric vias; and a die support, the semiconductor dies being disposed between the die support and the bridge structure, wherein a sidewall of the die support is coplanar with a sidewall of the bridge structure.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chiang Ting, Jian-Wei Hong, Sung-Feng Yeh
  • Publication number: 20240083763
    Abstract: The present disclosure provides a universal preparation method for in-situ growth of a layered double hydroxide (LDH) layer on a substrate surface, and belongs to the technical field of material synthesis. In the present disclosure, an LDH protective layer is grown in situ on a surface of a substrate by means of electrodeposition combined with hydrothermal treatment. Specifically, a seed crystal layer of the LDH is formed on the substrate surface by the electrodeposition, and then obtained LDH seed crystals are crystallized and grown by Ostwald ripening through the hydrothermal treatment. In this way, the LDH protective layer is formed in which an interlayer anion is a nitrate. The protective layer protects the substrate against corrosion. Moreover, since the interlayer anion is the nitrate, the protective layer can be exchanged with other corrosion-inhibiting anions, and is modifiable.
    Type: Application
    Filed: June 16, 2023
    Publication date: March 14, 2024
    Applicant: SHENZHEN UNIVERSITY
    Inventors: Shuxian HONG, Biqin DONG, Lei ZENG, Feng XING, Peiyu CHEN
  • Publication number: 20240079391
    Abstract: In an embodiment, a device includes: a first integrated circuit die comprising a semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first integrated circuit die, a surface of the gap-fill dielectric being substantially coplanar with an inactive surface of the semiconductor substrate and with a surface of the first through-substrate via; a dielectric layer on the surface of the gap-fill dielectric and the inactive surface of the semiconductor substrate; a first bond pad extending through the dielectric layer to contact the surface of the first through-substrate via, a width of the first bond pad being less than a width of the first through-substrate via; and a second integrated circuit die comprising a die connector bonded to the first bond pad.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 7, 2024
    Inventors: Chia-Hao Hsu, Jian-Wei Hong, Kuo-Chiang Ting, Sung-Feng Yeh
  • Publication number: 20240079364
    Abstract: Die structures and methods of forming the same are described. In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die face-to-face bonded to the lower integrated circuit die, the first upper integrated circuit die including a first semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and with a top surface of the first through-substrate via; and an interconnect structure including a first dielectric layer and first conductive vias, the first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate, the first conductive vias extending through the first dielectric layer to contact the top surface of the first through-substrate via.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 7, 2024
    Inventors: Chia-Hao Hsu, Jian-Wei Hong, Kuo-Chiang Ting, Sung-Feng Yeh
  • Publication number: 20240079936
    Abstract: A shaft voltage reduction structure is mounted on an electric machine having a bearing house and a rotor shaft rotatably connected together, and includes an electrically conductive main body, at least one electrically conductive bearing, and an electrically conductive shaft. The conductive main body is mounted to a bottom of the bearing house and includes a conductive shaft barrel projected from a center thereof. The conductive shaft barrel internally defines a shaft receiving hole, in which the conductive bearing is received. The conductive shaft includes a connecting end and a pivotal end connected to the rotor shaft and the shaft receiving hole, respectively. A shaft voltage across the rotor shaft of the electric machine is guided by the conductive shaft to release in a closed loop formed among the conductive main body, the conductive bearing and the bearing house, so as to reduce the shaft voltage of the electric machine.
    Type: Application
    Filed: April 26, 2023
    Publication date: March 7, 2024
    Inventors: Feng Liu, Kun-Cheng Yang, Qian-Hong Lei
  • Patent number: 11918547
    Abstract: Methods for treating excess pigmentation, including treatment of post inflammatory hyperpigmentation (PIH), are disclosed. The disclosed methods comprise administration of a composition comprising bakuchiol substantially free of furanocoumarins to a mammal. Compositions comprising bakuchiol and methods for their preparation are also disclosed.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: March 5, 2024
    Inventors: Mei Feng Hong, Qi Jia, Lidia Alfaro Brownell
  • Publication number: 20240050395
    Abstract: Disclosed are a deuterated oxophenylarsine, or a pharmaceutically acceptable salt thereof, and a pharmaceutical composition containing a pharmaceutically acceptable carrier and the deuterated oxophenylarsine. The deuterated oxophenylarsine can be used for treating and preventing cancers and related diseases.
    Type: Application
    Filed: March 31, 2021
    Publication date: February 15, 2024
    Inventors: Fude Huang, Wenan Wang, Feng Hong, Wanguo Wei, Jiangang Zhang, Changping Jiao, Luxiang Cao
  • Publication number: 20240044821
    Abstract: Disclosed is a combined X-ray fluorescence (XRF) analysis device. According to embodiments, the combined X-ray fluorescence analysis device includes: a ray emission channel including a ray source; an energy dispersive XRF (EDXRF) detection channel including an EDXRF detector, and the EDXRF detector is configured to detect fluorescence at different energies within a certain energy range in fluorescence emitted by an object irradiated by a ray from the ray emission channel; and a wavelength dispersive XRF (WDXRF) detection channel including a WDXRF detector, and the WDXRF detector is configured to detect fluorescence at one or more specific wavelengths in the fluorescence emitted by the object irradiated by the ray from the ray emission channel.
    Type: Application
    Filed: May 4, 2023
    Publication date: February 8, 2024
    Inventors: Xuena ZHANG, Feng HONG, Cuihuan WANG
  • Publication number: 20240024403
    Abstract: The present disclosure provides Diels-Alder adducts of chalcone and prenylphenyl moieties capable of modulating the activity of cannabinoid receptors, and to oligomers of flavan-3-ol capable of modulating fat absorption and storage. Such Diels-Alder adducts of chalcone and prenylphenyl moieties or oligomers of flavan-3-ol can optionally be used in combination with other weight management agents, such as anorectic agents, a lipase inhibitors, other cannabinoid receptor modulators, psychotropic agents, insulin sensitizers, stimulants, or satiety agents, as well as to methods of use thereof such as treating or preventing weight gain or obesity, promoting weight loss, appetite suppression, modifying satiety, or the like.
    Type: Application
    Filed: May 15, 2023
    Publication date: January 25, 2024
    Applicant: Unigen, Inc.
    Inventors: Lidia Alfaro Brownell, Byong-II Choi, Brandon Corneliusen, Mei-Feng Hong, Eu-Jin Hyun, QI Jia, Ping Jiao, Hyun-Jin Kim, Mi-Ran Kim, Tae-Woo Kim, Bo-Su Lee, Young-Chul Lee, Jeong-Bum Nam, Mesfin Yimam, Ji-Hye Hwang, Mi-Sun Oh
  • Publication number: 20230411964
    Abstract: A thermal power unit-flywheel energy storage cooperative frequency regulation control method and system is provided, which belongs to the technical field of a power grid. First, a real-time output increment of a thermal power unit is predicted, then a real-time frequency regulation power instruction of a flywheel energy storage system is determined based on the predicted real-time output increment of the thermal power unit, and finally the frequency regulation power instruction of the thermal power unit is determined by a difference adjustment coefficient of a governor and a grid frequency deviation. The thermal power unit and flywheel energy storage system is cooperatively controlled by frequency regulation based on the real-time output increment predicted value of the unit, which realizes self-adaptive adjustment of output of the flywheel energy storage system under dynamic working conditions, and improves the grid frequency stability and operation safety of the thermal power unit.
    Type: Application
    Filed: June 13, 2023
    Publication date: December 21, 2023
    Inventors: FENG HONG, LU LIANG, XINYI JIA, JUNHONG HAO, YANJUN DU, WEI WANG, FANG FANG
  • Publication number: 20230385521
    Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Yi-Lin CHUANG, Shih-Yao LIN, Szu-ju HUANG, Yin-An CHEN, Shih Feng HONG
  • Publication number: 20230385520
    Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Yi-Lin CHUANG, Shih-Yao LIN, Szu-ju HUANG, Yin-An CHEN, Shih Feng HONG
  • Patent number: 11823086
    Abstract: Disclosed is a membership analyzing method, including: obtaining data information of all members of a target group; classifying members with same first type information into a data set based on predetermined keywords; obtaining the type of first type information and data sets on condition that all members have been successfully classified into a corresponding data set, otherwise, if there is any remaining member failed to be classified into any data set, inputting data information of the remaining member into a predetermined classification model, to obtain the type of first type information and a data set of each remaining member; determining a tree structure of data sets based on the type of the first type information, and producing a graph for the tree structure; setting a same identification for the nodes of the same data set, and displaying second type information of each member in a display area.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: November 21, 2023
    Assignee: Beijing Hydrophis Network Technology Co., Ltd.
    Inventors: Weijie Zhou, Feng Hong, Min Huang, Wenbi Cai, Shanliang Xiong, Youpeng Wei
  • Patent number: 11806379
    Abstract: Compositions and methods for treatment of and maintaining the health of the liver are disclosed that include a mixture of plant extracts, wherein the plant extracts comprise at least one Myristica extract, at least one Astragalus extract, and at least one Schizandra extract. Compositions and methods for treatment of and maintaining the health of the liver are disclosed that include a mixture of plant extracts, wherein the plant extracts comprise at least one Myristica extract enriched for one or more lignans, including phenylpropanoids, dimers and polymers, at least one Astragalus extract enriched for one or more polysaccharides and triterpenoids, and at least one Schizandra extract enriched for one or more lignans and organic acids. Compositions and methods for treatment of and maintaining the health of the liver are disclosed that include a mixture of plant extracts, wherein the plant extracts comprise at least one Myristica extract, at least one Astragalus extract, and at least one Poria extract.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: November 7, 2023
    Assignee: Unigen, Inc.
    Inventors: Qi Jia, Mesfin Yimam, Ping Jiao, Mei Feng Hong, Breanna Moore
  • Publication number: 20230325573
    Abstract: A method includes providing a placing layout of the integrated circuit; generating a routed layout including a layout region with a systematic design rule check (DRC) violation; and performing a loop when the DRC the systematic DRC violation exists. The loop includes: generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe; extracting features of the placing layout to obtain extracted data; extracting features of the layout region with the systematic DRC violation to obtain extracted routing data; generating a plurality of aggregated-cluster models based upon the extracted data and the extracted routing data; selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models; and selecting the target placement recipe from a plurality of placement recipes to generate the adjusted routing layout.
    Type: Application
    Filed: May 31, 2023
    Publication date: October 12, 2023
    Inventors: SHIH-YAO LIN, YI-LIN CHUANG, YIN-AN CHEN, SHIH FENG HONG
  • Publication number: 20230236143
    Abstract: An X-ray analysis system is provided with multi-source design and an X-ray analysis method is provided with multi-source design. According to the embodiments, the X-ray analysis system includes a ray source including a plurality of ray generating devices that generate a ray; a detector that detects a signal generated due to an analyzed object being irradiated by the ray from the ray source; and a controller that controls the ray source, so that two or more ray generating devices in the ray source simultaneously generate corresponding rays to irradiate the analyzed object.
    Type: Application
    Filed: January 23, 2023
    Publication date: July 27, 2023
    Inventors: Xuena ZHANG, Feng HONG, Cuihuan WANG
  • Patent number: 11709987
    Abstract: A method of generating an integrated circuit includes providing a placing layout of the integrated circuit; generating a routed layout of the integrated circuit, the routed layout includes a layout region with a systematic design rule check (DRC) violation; generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in a plurality of placement recipes; extracting features of the placing layout to obtain an extracted data; extracting features of the layout region with the systematic DRC violation to obtain an extracted routing data; performing a training process upon the extracted data and the extracted routing data to generate a plurality of aggregated-cluster models; and selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Yao Lin, Yi-Lin Chuang, Yin-An Chen, Shih Feng Hong