Abstract: A file-based Read-ahead method employs asynchronous I/O processes to fetch Demand and Read-ahead data blocks from a disk (4), depending on their physical and logical sequentialities. When a file system (10) issues an I/O address to obtain data blocks from a file, it also determines the disk location of data blocks that are logically consecutive with the demanded data. The number of such data blocks to be determined in this process is accomplished in accordance with a dynamic Read-ahead method. If the data blocks are physically consecutive, a single I/O request is sent to a disk driver to obtain both the Demand data block and to Prefetch the Read-Ahead data block(s). If, instead, the data blocks are found not to be physically consecutive, a plurality of asynchronous disk I/O requests are issued so as to separately obtain the Demand and the Read-Ahead data blocks.

Abstract: A circuit to provide single phase clock signals having controlled clock skew to multiple integrated circuit chips is described. A source of single phase clock signals is supplied to a clock signal distribution tree of each integrated circuit. Phase comparison of signals produced by each clock distribution circuit tree provides a control signal for controlling the delay of a clock signal applied to a respective clock distribution tree. A gating circuit is disclosed which produces, in response to each clock signal produced by the clock distribution trees, an accurately controlled LOAD ENABLE and OUTPUT ENABLE signal.

Abstract: A file-based Read-ahead method employs asynchronous I/O processes to fetch Demand and Read-ahead data blocks from a disk (4), depending on their physical and logical sequentialities. When a file system (10) issues an I/O address to obtain data blocks from a file, it also determines the disk location of data blocks that are logically consecutive with the demanded data. The number of such data blocks to be determined in this process is accomplished in accordance with a dynamic Read-ahead method. If the data blocks are physically consecutive, a single I/O request is sent to a disk driver to obtain both the Demand data block and to Prefetch the Read-Ahead data block(s). If, instead, the data blocks are found not to be physically consecutive, a plurality of asynchronous disk I/O requests are issued so as to separately obtain the Demand and the Read-Ahead data blocks.

Abstract: A circuit to provide single phase clock signals having controlled clock skew to multiple integrated circuit chips is described. A source of single phase clock signals is supplied to a clock signal distribution tree of each integrated circuit. Phase comparison of signals produced by each clock distribution circuit tree provides a control signal for controlling the delay of a clock signal applied to a respective clock distribution tree. A gating circuit is disclosed which produces, in response to each clock signal produced by the clock distribution trees, an accurately controlled LOAD ENABLE and OUTPUT ENABLE signal.

Abstract: A least recently used cache replacement system in which the data cache is logically partitioned into two separate sections, demand and prefetch. A cache directory table and a least recently used table are used to maintain the cache. When a new demand data page is added to the cache, a most recently used (MRU) pointer is updated and points to this new page. When a prefetch page is added to the cache, the least recently used pointer of the demand section is updated with its backward pointer pointing to this new page. A cache hit on a demand of prefetch page moves that page to the top of the least recently used table. When a free page is needed in the cache, it is selected from the demand or prefetch sections of the memory based on a comparison of the demand hit density and the prefetch hit density so to maintain a balance between these two hit densities.

Abstract: A carry select adder may be used in which carry inputs to ripple adder stages are not fixed. The adder stage determines which of the two ripple adders of that stage has output the correct sum while the variable carry input is equal to a given value. Then the variable carry input value is switched to a different value and the adder stage determines the correct output sum from the other ripple adder. The adder performs self-checking by comparing these two sums to ensure that the output sum is accurate.