Abstract: A Totem-pole power factor corrector receives an input power source and convert the input power source into an output power source. The Totem-pole power factor corrector includes an input inductor, a fast-switching switch leg, a slow-switching switch leg, a resonant tank, and an output capacitor. The fast-switching switch leg includes a fast-switching upper switch and a fast-switching lower switch, and the fast-switching upper switch and the fast-switching lower switch are commonly coupled at a first middle node. The slow-switching switch leg is coupled in parallel to the fast-switching switch leg, and the slow-switching switch leg includes a slow-switching upper and a slow-switching lower switch. The resonant tank includes a resonant inductor and at least one resonant capacitor. A first end of the resonant inductor is coupled to the first middle node, and a second end of the resonant inductor is coupled to the at least one capacitor.

Abstract: A flying capacitor converter with zero-zero switching includes an input inductor, a fast-switching switch leg, a slow-switching switch leg, at least one flying capacitor, a resonant tank, and an output capacitor. The fast-switching switch leg included an upper leg having a plurality of upper switches and a lower leg having a plurality of lower switches. The slow-switching switch leg includes a slow-switching upper switch and a slow-switching lower switch, and the slow-switching upper switch and the slow-switching lower switch are coupled at a second middle node. The at least one flying capacitor is correspondingly coupled between the upper node and the lower node. The resonant tank includes a resonant inductor and a resonant capacitor, and the resonant inductor and the resonant capacitor are coupled in series between the first middle node and the second middle node.

Abstract: A development system and a method of an offline software-in-the-loop simulation are disclosed. A common firmware architecture generates a chip control program. The common firmware architecture has an application layer and a hardware abstraction layer. The application layer has a configuration header file and a product program. A processing program required by a peripheral module is added to the hardware abstraction layer during compiling. The chip control program is provided to a controller chip or a circuit simulation software to be executed to control the product-related circuit through controlling the peripheral module.

Abstract: A development system and a method of an offline software-in-the-loop simulation are disclosed. A common firmware architecture generates a chip control program. The common firmware architecture has an application layer and a hardware abstraction layer. The application layer has a configuration header file and a product program. A processing program required by a peripheral module is added to the hardware abstraction layer during compiling. The chip control program is provided to a controller chip or a circuit simulation software to be executed to control the product-related circuit through controlling the peripheral module.