Patents by Inventor Feng-Ji Tsai
Feng-Ji Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9508835Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ONO) structure under the first gate, forming an oxide structure covering the ONO structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.Type: GrantFiled: January 15, 2013Date of Patent: November 29, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Chung Chang, Shen-De Wang, Ya-Huei Huang, Feng-Ji Tsai, Chien-Hung Chen
-
Patent number: 9331185Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.Type: GrantFiled: October 3, 2014Date of Patent: May 3, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ya-Huei Huang, Shen-De Wang, Wen-Chung Chang, Feng-Ji Tsai, Chien-Hung Chen
-
Patent number: 9136276Abstract: A method for forming a memory cell structure includes following steps. A substrate including at least a memory cell region defined thereon is provided, and a first gate stack is formed in the memory cell region. A first LDD implantation is performed to form a first LDD at one side of the first gate stack in the memory cell region, and the first LDD includes a first conductivity type. A second LDD implantation is performed to form a second LDD at one side of the first gate stack opposite to the first LDD in the memory cell region, and the second LDD includes the first conductivity type. The first LDD and the second LDD are different from each other.Type: GrantFiled: April 18, 2014Date of Patent: September 15, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ya-Huei Huang, Sung-Bin Lin, Wen-Chung Chang, Feng-Ji Tsai, Yen-Ting Ho, Chien-Hung Chen
-
Publication number: 20150056775Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.Type: ApplicationFiled: October 3, 2014Publication date: February 26, 2015Inventors: Ya-Huei Huang, Shen-De Wang, Wen-Chung Chang, Feng-Ji Tsai, Chien-Hung Chen
-
Patent number: 8848454Abstract: A method for programming a non-volatile memory cell is described. The memory cell includes a substrate, a gate over the substrate, a charge-trapping structure at least between the substrate and the gate, and first and second S/D regions in the substrate beside the gate. The method includes performing a channel-initiated secondary electron (CHISEL) injection process to inject electrons to the charge-trapping structure.Type: GrantFiled: October 2, 2012Date of Patent: September 30, 2014Assignee: United Microelectronics Corp.Inventors: Feng-Ji Tsai, Shen-De Wang, Wen-Chung Chang, Ya-Huei Huang, Chien-Hung Chen
-
Patent number: 8837220Abstract: A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided. Two adjacent memory cells correspond to one bit and comprise a substrate, a first and another first doping regions, a second doping region, a charge trapping layer, a control gate, a first bit line, a source line and a second bit line different from the first bit line. A first and a second channel are formed. The charge trapping layer is disposed on the first and the second channels. The two adjacent memory cells are programmed by following steps. A first positive and negative voltages are applied to the control gate between the first and the second doping regions and the control gate between the second and the another first doping regions, respectively. A first voltage is applied to the source line.Type: GrantFiled: January 15, 2013Date of Patent: September 16, 2014Assignee: United Microelectronics Corp.Inventors: Shen-De Wang, Wen-Chung Chang, Ya-Huei Huang, Feng-Ji Tsai, Chien-Hung Chen
-
Publication number: 20140198574Abstract: A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided. Two adjacent memory cells correspond to one bit and comprise a substrate, a first and another first doping regions, a second doping region, a charge trapping layer, a control gate, a first bit line, a source line and a second bit line different from the first bit line. A first and a second channel are formed. The charge trapping layer is disposed on the first and the second channels. The two adjacent memory cells are programmed by following steps. A first positive and negative voltages are applied to the control gate between the first and the second doping regions and the control gate between the second and the another first doping regions, respectively. A first voltage is applied to the source line.Type: ApplicationFiled: January 15, 2013Publication date: July 17, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shen-De Wang, Wen-Chung Chang, Ya-Huei Huang, Feng-Ji Tsai, Chien-Hung Chen
-
Publication number: 20140197472Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ONO) structure under the first gate, forming an oxide structure covering the ONO structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.Type: ApplicationFiled: January 15, 2013Publication date: July 17, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wen-Chung Chang, Shen-De Wang, Ya-Huei Huang, Feng-Ji Tsai, Chien-Hung Chen
-
Publication number: 20140175531Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ya-Huei Huang, Shen-De Wang, Wen-Chung Chang, Feng-Ji Tsai, Chien-Hung Chen
-
Publication number: 20140092689Abstract: A method for programming a non-volatile memory cell is described. The memory cell includes a substrate, a gate over the substrate, a charge-trapping structure at least between the substrate and the gate, and first and second S/D regions in the substrate beside the gate. The method includes performing a channel-initiated secondary electron (CHISEL) injection process to inject electrons to the charge-trapping structure.Type: ApplicationFiled: October 2, 2012Publication date: April 3, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Feng-Ji Tsai, Shen-De Wang, Wen-Chung Chang, Ya-Huei Huang, Chien-Hung Chen