Abstract: The present invention provides a substrate supporting apparatus having a spin chuck and a plurality of locating pins. The spin chuck configured to support and rotate a substrate has a supporting surface. The locating pins are disposed at the periphery of the supporting surface for limiting the substrate horizontal displacement. The supporting surface defines a first annular region. The first annular region is divided into a plurality of pin regions and a plurality of non-pin regions. The pin regions and the non-pin regions are arranged alternatively in a circumferential direction of the first annular region. Each of the pin regions is corresponding to one locating pin. A plurality of Bernoulli holes are set in the first annular region and is configured as an uneven structure in the first annular region so as to supply stronger gas flow in the pin regions than in the non-pin regions.

Abstract: A liquid crystal antenna and a method for forming a liquid crystal antenna are provided. The liquid crystal antenna includes a first substrate; a second substrate opposite to the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate. A first conductive layer is disposed on a side of the first substrate facing toward the second substrate; a second conductive layer is disposed on a side of the second substrate facing toward the first substrate; the second conductive layer at least includes a plurality of radiation electrodes; an external metal layer is disposed on a side of the first substrate facing away from the liquid crystal layer; and the external metal layer is connected to a fixed potential.

Abstract: Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.

Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.

Abstract: A below-elbow prosthetic arm assembly includes a hand; an arm connected to the hand; a cylinder connected to the arm; and a string connected to the rear end of the cylinder. To start using the prosthetic arm, the user's amputated upper limb is enclosed by the cylinder and tied thereto with a string. The below-elbow prosthetic arm assembly further includes an expansion kit adapted to meet the user's needs in daily lives, learning and sports. The expansion kit is directly fitted to the hand. Function expansion is achieved without removing the hand. Therefore, the below-elbow prosthetic arm exhibits enhanced ease of use and minimizes the user's financial burdens which might otherwise arise from ordering customized prosthetic arms for use in different activities.

Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.

Abstract: In some embodiments, the present disclosure relates to method for forming an image sensor integrated chip. The method includes forming a first photodetector region in a substrate and forming a second photodetector region in the substrate. A floating diffusion node is formed in the substrate between the first photodetector region and the second photodetector region. A pick-up well contact region is formed in the substrate. A first line intersects the floating diffusion node and the pick-up well contact region. One or more transistor gates are formed on the substrate. A second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.

Abstract: A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.

Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a CMP stop layer is formed over the first ILD layer, a trench opening is formed by patterning the CMP stop layer and the first ILD layer, an underlying first process mark is formed by forming a first conductive layer in the trench opening, a lower dielectric layer is formed over the underlying first process mark, a middle dielectric layer is formed over the lower dielectric layer, an upper dielectric layer is formed over the middle dielectric layer, a planarization operation is performed on the upper, middle and lower dielectric layers so that a part of the middle dielectric layer remains over the underlying first process mark, and a second process mark by the lower dielectric layer is formed by removing the remaining part of the middle dielectric layer.

Abstract: A method includes performing a first lithography process using a first pattern of a first photomask to form a first photoresist pattern on a front side of a device substrate; performing a first implantation process using the first pattern as a mask to form first isolation regions in the device substrate; after performing the first implantation process, performing a second lithography process using a second pattern of a second photomask to form a second photoresist pattern on the front side of the device substrate, the second pattern being shifted from the first pattern by a distance less than the first pitch and in the first direction; performing a second implantation process using the second photoresist pattern as a mask to form second isolation regions in the device substrate and spaced apart from the first isolation regions; and forming pixels between the first and second isolation regions.

Abstract: A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.

Abstract: Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.

Abstract: A method includes forming a first photoresist layer on a front side of a device substrate and having first trenches spaced apart from each other. A first implantation process is performed using the first photoresist layer as a mask to form first isolation regions in the device substrate. A second photoresist layer is formed on the front side and has second trenches. A second implantation process is performed using the second photoresist layer as a mask to form second isolation regions in the device substrate and crossing over the first isolation regions. A third photoresist layer is formed on the front side and has third trenches spaced apart from each other. A third implantation process is performed using the third photoresist layer as a mask to form third isolation regions in the device substrate and crossing over the first isolation regions but spaced apart from the second isolation regions.

Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.